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asahi kasei [AK8850] AK8850 ntsc digital video decoder general description t he AK8850 decodes nt sc composite video, s-video and component video signals (525/625) into digital formats. digital output conforms to it u-r bt .601 and it u-r bt .656* ycrcb specif ications. t he AK8850 outputs a control signal to generate clocks sy nchroni zed w i th either horizontal sy nc or vertical sy nc signals. its clock rate is 27 mhz. an encoded vbid closed caption signal c an be extracted from the video signal and sent to an external pin on the AK8850. features nt sc-m composite signal and s-video signal decoder component video decoder for 525 / 625 sy stems ( betacam,mii,ebu n10 ) on-chip triple 10-bit adcs ( 27 mhz operation ) on-chip programmable gain amp ( pga ), rangi ng from 0 db to 12 db in 0.1 db / steps input-sy n chronized clock is generated by an external vcxo sub-carrier generation by digital sy nthesizer ( df s ) auto color control ( acc ) auto gain control ( agc ) adaptive 3-line y-c separation it u-r bt .656 format output ( 4:2:2 8- bit parallel output w i th eav / sav ) nt sc closed caption signal decoding function vbid program condition decoding function w ss program condition decoding function video aspect signal decoding function on line 16 and line 279 sleep function 6?channel analog inputs i2c control 3.3 v cmos 100-pin lqf p package note: * it u-r bt .656 spec may not be satisfi ed, as it is dependent upon input signal quality . rev.0 1 2002/01
asahi kasei [AK8850] analog multiplexer clamp pg a sy nc separator vref decimation f ilter sy nc-separatio n & agc info. & closed caption vbid extraction timing contorller & vco controller & registers clock module ain1 ain2 ain3 ain4 ain5 ain6 fbcap1 fbcap2 fbcap3 llpfc llpf y/ c separation (2d-3line or 1d-bpf) luma- processing & image ctrl (b righ t n e ss, c ontr a st etc.) chroma- processing & acc & image ctrl (hue ,s a t u r a t io n ) dfs ( c hr oma pll) d[7:0] 10-bit a dc halfclkout dvalid/vlock vsy nc hsy nc field frame0 frame1/csy nc extclp irefr1 10-bit a dc 10-bit a dc co m p o s ite y c /u v y v u v clk27mout microprocessor i/f nsig nstd u phase error 27mhz 13.5mhz sy nc1 sy nc2 sy nc3 clpcap1 clpcap2 clkinv output processing (level shifter & rec.656 formatter etc.) w i th buffer flpf flpfc clk ivcxo 1. f unctional block diagram c rev.0 2 2002/01 s i t e v i d e o s i g n a l i p u t ) 1 - 1 . s i g n a l p a t h ( c o m p o n avdd avss vrn vrp vco m sela s da scl /reset irefr2 vref dvss dvdd pd
asahi rev.0 3 2002/01 kasei [AK8850] analog multiplexer clamp pg a sy nc separator vref decimation f ilter sy nc-separatio n & agc info. & closed caption vbid extraction timing contorller & vco control l e r & registers ain1 ain2 ain3 ain4 ain5 ain6 fbcap1 fbcap2 fbcap3 llpfc llpf y/ c separation (2d-3line or 1d-bpf) luma- processing & image ctrl (b righ t n e ss, c ontr a st etc.) chroma- processing & acc & image ctrl (hue ,s a t u r a t io n ) dfs ( c hr oma pll) d[7:0] 10-bit a dc halfclkout dvalid/vlock vsy nc hsy nc field frame0 frame1/csy nc extclp irefr1 co m p o s ite co m p o s ite c u v clk27mout microprocessor i/f nsig nstd phase error 27mhz 13.5mhz sy nc1 sy nc2 sy nc3 clpcap1 clpcap2 clkinv output processing (level shifter & rec.656 formatter etc.) w i th buffer y y co m p o s ite flpfc flpf clock module clk ivcxo 1-2. signal path ( yc signal input ) avdd avss vrn vrp vco m sela s da scl /reset irefr2 vref dvss dvdd pd
asahi kasei [AK8850] y y c analog multiplexer clamp pg a sy nc separator vref decimation f ilter sy nc-separatio n & agc info. & closed caption vbid extraction timing contorller & vco control l e r & registers clock module ain1 ain2 ain3 ain4 ain5 ain6 fbcap1 fbcap2 fbcap3 llpfc llpf rev.0 4 2002/01 1 - 3 . s i g n a l p a t h ( c o m p o n e n t s i g n a l i n p u t ) avdd avss vrp vco m vrn sela s da scl /reset luma- processing & image ctrl (b righ t n e ss, c ontr a st etc.) chroma- processing & acc & image ctrl (hue ,s a t u r a t io n ) dfs ( c hr oma pll) d[7:0] 10-bit a dc halfclkout dvalid/vlock vsy nc hsy nc field frame0 frame1/csy nc extclp irefr1 10-bit a dc y c y c u v clk27mout microprocessor i/f nsig nstd phase error 27mhz 13.5mhz sy nc1 sy nc2 sy nc3 clpcap1 clpcap2 clkinv output processing (level shifter & rec.656 formatter etc.) w i th buffer flpfc flpf clk ivcxo dvss dvdd pd vref irefr2 timing contorller clock mdl flpfc llpf halfclkout clk27mout nsig nstd phase error clkinv llpf clk ivcxo
asahi kasei [AK8850] rev.0 5 2002/01
asahi kasei [AK8850] 2. pin assignment avdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ain1 avss sync1 avss ain2 avss sync2 avss ain3 avss sync3 avss avss avss ain4 avss ain5 avss ain6 avss test pd test test test scl sda sela dvss field hsync vsync dvdd dvss d7 d6 dvdd dvss d5 d4 dvdd dvss d3 d2 dvdd dvss d1 d0 dvdd /reset clkinv ud9 ud8 ud7 ud6 ud5 dvss dvdd n std dvss n sig clk27mout dvdd halfclkout frame0 frame1 dvss dvdd dvalid/vlock ud4 ud3 ud2 ud1 ud0 avdd avss clpcap1 fbcap1 vrp vrn vcom irefr2 irefr1 ivcxo vrefout flpfc flpf llpfc llpf avss avdd avss extclp dvdd cl k dvss clpcap2 fbcap2 fbcap3 rev.0 6 2002/01
asahi kasei [AK8850] 3. pin f unctional description pin number identification i/o description 2 scl i i2c bus clock 3 sda i/o i2c bus data (open collector ) 4 sela i i2c bus address selector 6 f i e l d o f i eld identify low even high odd 7 hsync o hsync t i ming output pin 8 v s y n c o vsync t i ming output pin. (it is possibl e to output v_blank signal (vd) by setting a register) 11 d7 (msb) o decoded data output pin (msb) 1 2 d 6 o 1 5 d 5 o 1 6 d 4 o 1 9 d 3 o 2 0 d 2 o 2 3 d 1 o decoded data output pin 24 d0 (lsb) o decoded data output pin (lsb) 3 1 d v a l i d / v l o c k o active video t i ming signal (720 pixel) it can also output vlock status by setting a register. 3 4 f r a m e 1 / c s y n c o 3 5 f r a m e 0 o w hen a standard signal is input, a color frame signal is output. w hen a non-standard signal input, this pi n outputs a timing signal that is toggled every 525/625 lines. f r ame1 pin can output the cys nc signal by setting a register. 3 6 h a l f c l k o u t o w hen rec.656 data is output, this signal identifies the signal as y or c. (t his rate is about 13.5mhz) 3 9 c l k 2 7 m o u t o output t i ming of output data (about 27mhz) 40 nsig o w hen no-signal is input this pin goes high. 41 nst d o w hen non-standard signal is input, this pin goes high. 49 clkinv i t h is pin decides t he polarization of clk27mout . 5 0 / r e s e t i reset signal input pin. (low active) after pow e r up or pow er dow n mode, reset signal should be low at least 10msec. 52 clk i input 27mhz clock. 54 ex t c lp i/o ex ternal clamp timing input pin. 58 llpf o connect loop f ilter for line lock clock. 59 llpf c o connect capacitors for line lock clock. 60 f l pf o connect loop f ilter for f r ame lock clock. 61 f l pf c o connect capacitors for f r ame lock clock. 6 2 v r e f o u t o internal voltage reference output pin. t e rminate w i th 0.1uf or la rger capacitor betw een avss. 6 3 i v c x o o control voltage output pin for the external vcxo. connect via a resistor to avss. 6 4 i r e f r 1 o t e rminate w i th 13k ? ?
asahi kasei [AK8850] 70 fbcap2 o t e rminate 0.033uf capacit or betw een avss. (for clamp level) 71 fbcap1 o t e rminate 0.033uf capacit or betw een avss. (for clamp level) 72 clpcap2 o t e rminate 0.1uf capac itor betw een avss. (for clamp) 73 clpcap1 o t e rminate 0.1uf capac itor betw een avss. (for clamp) 7 6 a i n 1 i 8 0 a i n 2 i 8 4 a i n 3 i 9 1 a i n 4 i 9 3 a i n 5 i 9 5 a i n 6 i analog video signal input pin. t he si gnal should be input through a 0.1uf capacitor w i th -6db gain. 7 8 s y n c 1 i 8 2 s y n c 2 i 8 6 s y n c 3 i analog video signal input pin for the internal clamp pulse generator. t h is signal should be input through a 0.1uf capacitor w i th 0db gain. 9 8 p d i pow e r dow n control pin. w hen this pin becomes high, the AK8850 enters a pow er dow n state. w hen returning fr om pow er dow n mode, AK8850 requires reset sequence. 56,75,88 avdd p analog pow er supply (3.3v) pin. 55,57,74, 77,79,81, 83,85,87, 89,90,92, 94,96,96 avss g analog ground pin. 9,13,17, 21,25,32, 37,42,53 dvdd p digital pow er supply (3.3v) pin. 5,10,14, 18, 2,33, 38,43,51 dvss g digital ground pin. 26,27,28, 29,30,44, 45,46,47, 48 ud[9:0] i/o t hese pins are for test purpose. t hese pins should be nc. 1,44,45, 46,47,48, 97,99, 100 t est i t hese pins are for test purpose. connect to the dvss. rev.0 8 2002/01
asahi kasei [AK8850] 4. electrical s pecifications 4-1. absolute maximum ratings item min. max unit supply voltage vdd dvdd, avdd 0.3 4 . 5 v input pin voltage (vin) 0.3 vdd + 0.3 v input pin current (iin) 1 0 1 0 m a storage t e mperature 4 0 1 2 5 note) each ground pin ( dvss,avss) is equal to 0 v (voltage reference ). 4-2. recommended operating conditions item min. ty p . max . unit 3 . 0 3 . 3 3 . 6 v supply voltage avdd dvdd 3 . 0 3 . 3 3 . 6 v operating t e mperature 1 0 8 5 * * note) * each ground pin ( dvss,avss) is equal to 0 v (voltage reference ). ** assumes mounting on a 4-lay e r pcb > 100mm x 100mm x 1.6mm w i th w i ring density greater than 60%. 4-3dc characteristics ( dvdd=a v dd=3. 0 ~ 3.6 v at room temperature ) item sy mbol min. ty p . max . unit condition digital input high volt a g e v i h 0 . 7 v d d v digital input low volt age vil 0.3vdd v digital input leak current iil 1 0 u a digital output high voltage voh 2.4 v ioh = 400ua digital output high voltage vol 0.4 v iol = 1.2ma i 2 c input high voltage i 2 c (sda, scl) v i h c 0 . 7 v d d v i 2 c input low voltage i 2 c (sda, scl) vilc 0.3vdd v i 2 c (sda) l volc 0.4 v iolc = 3ma 4-4. ac characteristics item sy mbol min. ty p . max . unit condition digital maximum load capacitance 1 5 4 0 pf rev.0 9 2002/01
asahi kasei [AK8850] 4-5. analog characteristics and pow e r dissip a tion selector and clamp (a vdd= 3. 3v , room t e mperature) item sy mbol min. ty p . max . unit condition maximum input range (ain1 ain6) v i m x 1 . 2 0 1 . 2 8 v pp pga gain 0db composite, luminance signal clamp level v y c p 0 . 7 0 v c/u/v signal clamp level v c c p 1 . 3 4 v clamp current clpi 70 u a isolation betw een adc - 60 d b 5.5mhz pga (a vdd= 3.3v , room t e mperature) item sy mbol min. ty p . max . unit condition m i n . g a i n g m n 0 d b m a x g a i n g m x 1 2 d b g a i n s t e p gst 0 . 0 9 4 d b relative gain accuracy erp 1 l s b adc (a vdd= 3.3v , room t e mperature) item sy mbol min. ty p . max unit condition r e s o l u t i o n r e s 1 0 b i t s operating clock f r equency f s 27 mhz integral non linearity inl 2.0 4 . 0 l s b fs= 2 7 m h z differential non linearity dnl 0.8 2 . 0 l s b fs= 2 7 m h z s / n s n 54 db fin=1mhz ain= 1db fs=27mhz s / ( n + d ) s n d 51 db fin=1mhz ain= 1db fs=27mhz pow e r consumption (dvdd= a v dd= 3.3v , room t e mperature) item sy mbol min. ty p . max unit condition compensation current (active) digital + analog analog digital 216 71 145 280 ma ma ma 3ch operating 25pf load, color bar input p o we r d o wn c u r r e n t mode 1 digital + analog analog digital mode 2 digital + analog analog digital 58 22 36 0.01 0.01 0.01 75 0.2 ma ma ma ma ma ma mode 1: set by register mode 2: set by pd pin *it requires several second from mode 2 pow er dow n mode to active mode. rev.0 10 2002/01
asahi kasei [AK8850] 4-6. ac t i ming ( dvdd= 3.0 ~ 3.6 v at 25 deg. c ) 4-6-1 clock input vih vil fsy s clk tclkl tclkh 1/2 level of vhi and vil item sy mbol min. ty p . max unit c l k f s y s c l k 2 7 m h z clk pulse w i dth (high) tclkh 15 nsec clk pulse w i dth (low ) tclkl 15 nsec stability of clock 1 0 0 p p m 4-6-2 output dat a t i ming ( d7 ~ d0 ) 4-6-2-1 clkinvpin = l tohd1 vil halfclkout vih vil d7:0] cb/cr y vil clk27mout vih vih todl1 item sy mbol min. ty p . max . unit note output data delay t i me todl1 25.0 nsec output data hold time t o h d 1 3 . 0 n s e c cl 25pf rev.0 11 2002/01
asahi kasei [AK8850] 4-6-2-2 clkinvpin = h tohd2 vil halfclkout vih v ih vil d7:0] cb/cr y todl2 vil tdhclk clk27mout vih item sy mbol min. ty p . max . unit note output data delay t i me todl2 25.0 nsec output data hold time t o h d 2 3 . 0 n s e c cl 25pf 4-6-3 output data t i ming ( dvalid /vsync/hsync/field/frame0/frame1 ) 4-6-3-1 clkinvpin = l tohd3 vih clk27mout vih dv alid vsy nc/vd hsy nc field frame output control register dv alid=l vsy nc=l hsy nc =l field=l frame=l vil dv alid vsy nc/vd hsy nc field frame tohd3 vih clk27mout output control register dv alid=h vsy nc=h hsy nc =h field=h frame=h item sy mbol min. ty p . max . unit note output data hold time t o h d 3 3 . 0 n s e c c l 25pf rev.0 12 2002/01
asahi kasei [AK8850] 4-6-3-2 clkinvpin = h vil clk27mout tohd4 vih dv alid vsy nc/vd hsy nc field frame output control register dv alid=l vsy nc=l hsy nc =l field=l frame=l output control register dv alid=h vsy nc=h hsy nc =h field=h frame=h vil dv alid vsy nc/vd hsy nc field frame vil clk27mout tohd4 item sy mbol min. ty p . max unit note output data hold time tohd4 3.0 nsec cl 25pf rev.0 13 2002/01
asahi kasei [AK8850] 4-6-4 output dat a t i ming ( clk27mout , dv alid signal, d7~ d 0 relation ) 4-6-4-1 clkinvpin l and output control register dvalid-bit= l 4-6-4-3 clkinv pin h and output control register dvalid-bit= l tohd1 d[7:0] vil clk27mout vih y0 cb0 cr359 cr0 tohd2 y 719 dv alid vil vih d[7:0] vil clk27mout vih y0 cb0 cr359 cr0 tohd2 y 719 dv alid tohd1 vil vih vih rev.0 14 2002/01
asahi kasei [AK8850] 4-6-5 reset t i ming ( initialization ) reset signal ( reset signal should be held low state for 10msec or longer) pres /reset item sy mbol min. ty p . max . unit note /reset pulse w i dth p r e s 1 0 m s e c note sy stem control pins (sela, clkinv, pd etc.) remain in their states for at least 10 clock cy cles before/after a reset signal input. 4-6-6 pow e r-dow n / up sequence vil vil /reset pd clk hres sres item sy mbol min. ty p . max . unit note reset pulse w i dth (setting pd mode) s r e s 1 0 0 c l k from clk rising edge rese pulse w i dth (returning from pd mode) h r e s 1 0 m s e c note) after pd pin becomes high (pow er dow n state), /reset pin status is irrelevant. rev.0 15 2002/01
asahi kasei [AK8850] 4-6-7 i2c bus input & output t i ming ( scl 400khz cy cle mode ) (1) t i ming 1 tr tlow sd a tbuf thd:st a tf tr tf tsu:sto tsu:st a scl 0.7vdd 0.3vdd 0.7vdd 0.3vdd item sy mbol min. max . unit bus free time tbuf 1.3 usec hold time (start condition) thd:sta 0.6 usec clock pulse low time tlow 1.3 usec input signal rise time tr 300 nsec input signal fall time tf 300 nsec setup time(start condition) tsu:sta 0.6 usec setup time(stop condition) tsu:sto 0.6 usec all the figures show n above are not def ined by the AK8850 but are defined by i 2 c bus standard. please see the i 2 c bus standard for further details (2) timing 2 sda thd:dat tsu:dat thigh scl 0.7vdd 0.3vdd 0.7vdd 0.3vdd item sy mbol min. max . unit data setup time tsu:dat 100(1) nsec data hold time thd:dat 0.0 0.9(2 usec clock pulse high time thigh 0.6 usec (1) in c a s e of normal i 2 c bus mode tsu:dat 250nsec (2) using under minimum tlow, this value must be satisfied. rev.0 16 2002/01
asahi kasei [AK8850] 5. output signal t i ming description 5-1. nt sc input vertical sy nc timing, field signal and frame signal timing relati ons are show n below . t he logic st ates of hsync/vsync/field/fra me can be altered via register settings. depending on the register setting either vsync or vd signal is available. f i eld output and f r ame output signals change states on the risi ng edge of csync just before t he 0.5h delay period that is controlled by the output control regist er. t he 0.5h delay timing is show n on page 18. note) frame timing signal output is as show n above w hen standard signals are input to t he AK8850. if a non-standard signal is input to AK8850, the number of color frame is not guaranteed. when the input signal changes from non-standard to standard, that the fram e timing signal may not change fo r 512 lines (max) as the ak88 50 sy nchronizes to the input video signal. vsync field even odd even odd 52 52 52 1 2 3 4 5 6 7 8 9 10 11 frame field frame vsync (low) field even odd frame 26 26 26 26 26 26 27 27 26 26 27 27 27 26 even odd field frame vsync (high 26 26 26 26 26 26 27 27 26 26 27 27 27 26 hsync csync csync hsync 52 52 52 1 2 3 4 5 6 7 8 9 10 11 csync hsync vsync csync hsync vd vd vd vd rev.0 17 2002/0
asahi kasei [AK8850] 5-2. f i eld/f r ame signal output t i ming diagram w i th nt sc signal input ( csync & f i eld/f r ame0/f rame1 relationship ) w hen [output control register] f f d ela y -bit = 0: at [output control register] f f d ela y -bit = 1: csync field even odd even odd 5 2 5 2 5 2 12 3 4 56789 1 0 1 1 frame field frame (low) field even odd frame 26 26 26 26 26 26 27 27 26 26 27 27 27 26 even odd field frame (high csync csync 5 2 5 2 5 2 1 2 3 4 56789 1 0 1 1 csync 26 26 26 26 26 26 27 27 26 26 27 27 27 26 csync 5 2 5 2 5 2 12 3 4 56789 1 0 1 1 field even odd frame even odd field frame (low) even odd field frame (high field even odd frame csync 5 2 5 2 5 2 1 2 3 4 56789 1 0 1 1 csync 26 26 26 26 26 26 27 27 26 26 27 27 27 26 csync 26 26 26 26 26 26 27 27 26 26 27 27 27 26 rev.0 18 2002/0
asahi kasei [AK8850] 5-3. output signal t i ming diagr am ( ccir625 component input ) t he vert i cal sy nc signal, field signal and frame signal timing rela tionships are show n. t he logi cal state of hsync/vsync/field/ f r ame can be altered by using register settings. either vsync or vd output signals are av ailable on the vsync output pin, depending upon t he register setting. t he field output and the f r ame output si gnals change state on the rising edge of the csync, prior to the 0.5h delay period that is controlled by the output control register . f i eld/f r ame output timings are show n on pages 20 and 21. frame (low) hsync vsync vd field even odd hsync vsync vd frame field even odd frame hsync vsync even odd field hsync vsync vd even odd field frame (high vd csync 62 62 62 62 62 1 2 3 4 5 6 8 7 csync 31 31 31 31 31 31 31 31 31 30 31 32 30 32 csync 1 62 62 62 62 62 62 2 3 4 5 6 8 7 csync 31 31 31 31 31 31 31 31 31 30 31 32 30 32 62 rev.0 19 2002/0
asahi kasei [AK8850] 625 component signal output t i ming diagram ( c sync & f i eld/f r ame0/f rame1 relationship ) at [output control register] f f d elay-bit= 0 csync 620 621 622 623 624 625 1 2 3 4 5 6 8 7 field even odd frame0 frame0 (low) even odd field csync 311 312 313 314 315 316 317 318 310 309 319 321 308 320 field even odd frame0 csync 1 620 621 622 623 624 625 2 3 4 5 6 8 7 even o dd field frame0 (high) csync 311 312 313 314 315 316 317 318 310 309 319 321 308 320 frame1 (low) frame1 (low) frame1 (low) frame1 (low) csync 620 621 622 623 624 625 1 2 3 4 5 6 8 7 field even odd frame0 frame1 (high) frame0 (low) even odd field csync 311 312 313 314 315 316 317 318 310 309 319 321 308 320 frame1 (high) field even odd frame0 csync 1 620 621 622 623 624 625 23 4 5 6 8 7 frame1 (high) even o dd field frame0 (high) csync 311 312 313 314 315 316 317 318 310 309 319 321 308 320 frame1 (high) 5-5 625 component signal output t i ming diagram ( csync & f i eld/f r ame0/f rame1 relationship ) w hen [output control register ] f f d elay-bit = 1 rev.0 20 2002/0
asahi kasei [AK8850] csync 620 621 622 623 624 625 1 2 3 4 5 6 8 7 field even odd frame0 frame0 (low) even odd field csync 311 312 313 314 315 316 317 318 310 309 319 321 308 320 field even odd frame0 csync 1 620 621 622 623 624 625 2 3 4 5 6 8 7 even o dd field frame0 (high) csync 311 312 313 314 315 316 317 318 310 309 319 321 308 320 frame1 (low) frame1 (low) frame1 (low) frame1 (low) csync 620 621 622 623 624 625 1 2 3 4 5 6 8 7 field even odd frame0 frame1 (high) frame0 (low) even odd field csync 311 312 313 314 315 316 317 318 310 309 319 321 308 320 (high) field even odd frame0 csync 1 620 621 622 623 624 625 23 4 5 6 8 7 frame1 (high) even o dd field frame0 (high) csync 311 312 313 314 315 316 317 318 310 309 319 321 308 320 frame1 (high) frame1 rev.0 21 2002/0
asahi kasei [AK8850] 6. f unctional summary 6-1. clock 1. line locked clock mode: an operating mode w here the devic e operates using a clock sy nchronized w i th the horizontal sy nc signal for each line. 2. f r ame locked clock mode: t he device operates using a clock sy nchronized w i th the vertical sy nc signal at each f r ame. 3. f i xed clock mode: an external clock is used. t hese clock modes are set w i th the control 2 register . since both the line locked and f r ame locked modes use an input-signal sy nchronized clock, it u-r bt .656* compatible output is available, although input signal quality may prevent full it u-r bt .656 compatibility . 6-2. analog interface t he AK8850 decodes nt sc-m compatible composite vi deo signals, s-video and component signals. f o r ccir625 sy stems, only the component signal is us ed. registers control setup selection. 6-3. input signals t he device accepts nt sc-m composite, s-video,, composite ( betacam,mii ) and 625 component signals ( ebu n10 ). required input signal quality is as follow s . 6-3-1 composite ,s video input signal quality item input range unit condition video signal input level 6 db color burst input level 10 db video signal should be input w i th -6db level (divided be a resistor), and through 0.1uf capacitor. 6-3-2. supporting signal characteri stics for composite and s-video signals item process lack of hsync running w i th self timing lack of vsync running w i th self-timing. when vsync is absent for tw o consecutive cy cles, the AK8850 identifies this as a ?no-signal? state and sets the nsig pin high. b/w video signal input set b/ w mode using the register. 6-3-3. component input signal a standard signal is applied in component decode mode. s upported component signal condi tions are listed below . unit [mv] input video source sy nc level luminance (setup level) luminance level (max) luminance (range) u/v (range) note betacam (w /o setup) 2 8 6 0 7 1 4 7 1 4 504 luminance 100% u/v 100% level betacam (w ith 7.5% setup) 2 8 6 5 3 . 6 7 1 4 6 6 0 . 4 350 luminance 100% u/v 75% level mii (w /o setup) 3 0 0 0 7 0 0 7 0 0 350 luminance 100% u/v 100% level mii (w ith setup ) 3 0 0 5 2 . 5 7 0 0 6 4 7 . 5 243 luminance 100% u/v 75% level 625 sy stem (ebu n10) 3 0 0 0 7 0 0 7 0 0 350 luminance 100% u/v 100% level 6-4. analog input signal processing input selector : -60 db ( inter-channel isolation ) pga : 0 ~ 12 db ad converter : operates at 27 mhz line-lock or frame-lock pll clo cks are used in normal operation. rev.0 22 2002/01
asahi kasei [AK8850] 6-5. y/c separation f unction adaptive y/c separation: adaptive y/c separation enables adjustment of the chroma signal bandw id th. adaptive y/c separation can also be fixed to either 3-line 2 dimensional y/c s eparation or single dim ension y/c separation. 6-6. output signal bandw idth at composite signal input, luminance signal bandw idth : dc ~ 5.75 mhz + 0.5 /- 1.5 db chroma signal bandw idth : + / - 500 khz ~ + / - 1 mhz ( -3 db ) ( 3 ranges selectable ) at component signal input, luminance signal bandw idth : dc ~ 5.75 mhz + 0 .5 / -1.5 db chroma signal bandw idth : dc ~ 5.75 mhz + 0 .5 / -1.5 db 6-7. v i deo quality control f unction contrast, brightness, hue and color saturation levels are adjustable. no hue adjustment is possible w hen a component video signal is input. 6-8. output interface it u-r bt .601 compatible signal output levels decoded data is output in it u-r bt .656 fo rmat ( depends on the input signal quality ). ability to detect signals during active video peri od using hsync/vsync ( field )/ dvalid signals 8-bit output at 27 mhz rate 6-9. other f unctions black level signal is output w hen no signal is applied ( y = 16cb,cr = 128 ) ?lack of signal? input detection i2c bus interface ( 400 khz ) pow e r save mode closed caption, vbid, w ss and vi deo aspect ratio decoding f unctions. rev.0 23 2002/01
asahi kasei [AK8850] rev.0 24 2002/01 7. f unctional det a ils 7-1. analog signal processing block diagram from digital block t o digital block clock module (27mhz generator 13.5mhz generator) clk mode select reset clk13.5m pga_gain [6:0] x 3 y data[9:0] c data[9:0] / cb data[9:0] input_sel vref vrp v com v rn clk clamp_pulse_sel cr data[9:0] clamp1 _ lev [ 1:0 ] iref_r1 clk27m mux sy nc separaor ( c lamp pulse generator) extclp clamp1 clamp2 clamp3 composite y c/pb pr selector a in1 a in2 a in3 a in4 a in5 a in6 10-bit adc2 10-bit adc1 10-bit adc3 pg a2 0.1db/step 0-12db pg a1 0.1db/step 0-12db pg a3 0.1db/step 0-12db fbcap1 fbcap2 fbcap3 llpf flpf sy nc1 sy nc2 sy nc3 avdd avss clpcap1 clpcap2 vref irefr2 llpfc flpfc ivcxo
asahi kasei [AK8850] 7-2. analog signal process f unctional s pecifications 7-2-1 . i n p u t s i g n a l s e l e c t o r m o d u l e t he AK8850 has six (6) input pins. t he input signal sele ctor module selects one of the video sources. t he video sources available are single-pin com posite, 2-pin y / c and 3-pin component signals. a video source to be decoded is selected by the [input signal select regist e r]. t he ty pe of video signal to be decoded is set by the [input video st andard regist e r]. composit e signal input : t h is input is digitized by the clamp1, pga1 and adc1 in the analog signal processing block diagram. w hen decoding composite video, the adc2 and adc3 blocks can be plac ed in pow er save mode by programming the [ power save regist e r]. y/c signal (s-video ) input : t he y-signal is digitized by the clamp1, pga1 and adc1 as in the composite signal input case. t he c signal is digitized by the clamp2, pga2 and adc2. t he adc3 blo ck can be placed in pow e r save mode by programming the [ power save regist e r ]. component signal input : in this case, the y signal is digitized by the clamp1, pg a1 and adc1 as in the composite signal input case. t he pb signal is digitized by the clamp2, pga2 and adc2, w h ile t he pr signal is digitized by the clamp3, pga3 and adc3. description of the input signal-ty pe set regist er and input signal select control register: t he input signal ty pe is set by the [ input video st a ndard regist e r ] and input signal path is selected by the [ input signal select regist e r ]. [input video standard register] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r e s e r v e d nent b / w set u p v s 3 v s 2 v s 1 v s 0 default value 0 0 0 0 0 0 0 0 [input signal select register] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r e s e r v e d r e s e r v e d s y n c i n 1 s y n c i n 0 i n s e l 3 i n s e l 2 i n s e l 1 i n s e l 0 default value 0 0 0 1 0 0 0 1 [ vs3 : vs0]-bit and nent -bit setting are also described. [input video standard register ] [vs3:vs0]-bit setting [vs3:vs0]-bit input signal source note 0 0 0 0 n t s c 1111 component 625 (ebu n10) setup-bit : set up-bit setup or no-setup note 0 no setup in 1 w i th setup signal in b/w - bit : for black and w h ite video signal b/w-bit b/w signal or not note 0 color video signal 1 black and w h ite video signal yc separation function turns off rev.0 25 2002/01
asahi kasei [AK8850] nent -bit : setting for component signal input nent -bit signal source of component note 0 mii 300mv sy nc level 1 betacam 286mv sy nc level (supplement) t here are 3 categories of video signals w h ic h are summarized in t able 7-2-1-1 below . classify ing signal source nt sc composite nt sc yc mii component 525-lines sy stem betacam component no. of lines in a f r ame 625-lines sy stem 625 (ebu-n10) component nt sc composite nt sc yc 286mv sy nc level (40ire ) betacam mii component sy nc level 300mv sy nc level 625 (ebu-n10) component t a b l e 7-2-1-1 rev.0 26 2002/01
asahi kasei [AK8850] the i nput signal path ( input signal setting) is selected by [ inse l3 : insel0 ]-bits ( bit - 3:bit 0 ) in the [ input signal select regist e r]. t he upper 2-bits ( insel3 : insel2 ) ident ify composite /yc and component signals. [insel3:insel0] (bit3:bit0) signal select [0,0,0,0] no signal is selected. [0,0,0,1] composite signal is input from ain1 (default) [0,0,1,0] composite signal is input from ain2 [0,0,1,1] composite signal is input from ain3 [0,1,1,0] y-signal from ain2 c-signal from ain4 [0,1,1,1] y-signal from ain2 c-signal from ain4 [1,0,1,1] y-signal from ain3 u-signal from ain5 v-signal from ain6 as show n in the above table ,the ak 8850 accepts follow i ng 4 input signals:
asahi kasei [AK8850] 7-2-2. clamp t he clamp function stabilizes the ac -coupled video input signal level. t he AK8850 utilizes both an analog clamp circuit and a digital clamp circuit. w hen the composite and y signals (s-video, component y signal ) are input, the sync-t i p level or pedest al level of composite signal and luminance signal ( y ) are clamped. t he digitized input signal data is further signal-processed and clamped to the pedest al level( digital pedestal clamp ). clamp functions take place during the clamp pulse , as described below , in (1) sync separat ion funct ion. t he clamp interval is equal to the h sync interval (approximately 15 khz ). both the c and pb/pr signals are clamped at the sync-t i p timing of the luminance signal. (1) sync separat ion funct ion( clamp timing pulse generation ) in order to separate the sync signal of the target signal, the clamp t i ming pulse is used to clamp the input signal to a pre-determined level w h ich is fed back vi a the ain pin. t o generate a clamp ti ming pulse ,select one of the sync1 / sync2 / sync3 input signals by setting [ syncin1 : syncin0] of the ( input signal select regist e r). t he selected signal must be a signal w h ic h corresponds to ain1~ ain6 signals. t he separated sync signal is used for the clamp timing. sy nc-separation is done by slicing approx imately 70 mv positive point ( default value ) from the sync-t i p level. as described above, the clamp timing pul se is generated based on the separated signal ( sync det ).t he slice point is adjustable by register settings. rev.0 28 2002/01
asahi kasei [AK8850] ( 1-1) sync-t i p clamp t i ming pulse t he start point and pulse w i dth of the sync-t i p timing pulse is set by the [clamp t i ming 1 cont rol regist e r ]. t he start point of the sync-t i p timing pulse is set by [s clpst at 2 : sclpst at 0 ]-bit of the [ clamp t i ming 1 cont rol regist e r ] as show n below . t he clamp period ( pulse w i dth ) is set by [sclpw idt h 3 : sclpw i dt h 0 ]-bit of the [ clamp t i ming 1 cont rol regist e r ]. clamp pulse point and pulse w i dth setting is further de scribed in item( 1-6 )sync-separat ion relat e d regist e r descript ion. internal sy (syncdet input video signal location of sy n (ain1/ain2/ain3) 1clock = 37nsec a fter lpf sy nc1/2/3 input sy nc (hsy nc) r=620 c=510pf lpf constance 380nsec ( 2 + [ sclpstat2:sclpstat0 ] -bit ) c l ocks sy nctip clamp timing pulse [sc l pw id t h 3: sc lpw i d t h 0 ]-bit c l ocks 380nsec + (2 + [scl pst a t 2:scl pst a t 0] -bit) clocks 70mv (default a fter sy ncseparation nc reference ) rev.0 29 2002/01
asahi kasei [AK8850] ( 1-2 ) pedest al clamp t i ming pulse t he AK8850?s clamp point is initially set to the sync-t i p leve l. it is possible to clamp it at the pedestal point by changing a register value. t he start point of the pedestal clamp timing pulse is set by [ pclpst at 2 : pclpst at 0 ]-bit of the [ clamp t i ming 2 cont rol regist e r] as show n below . t he clamp period ( pulse w i dth ) is set by [ pclpw i dt h3 : pclpwidt h 0]-bit of t he [ clamp t i ming 2 cont rol regist e r ]. sync-separat ion relat e d regist e r descript ion. during the serrat ion pulse period, if no syncdet falli ng edge is detected before t he start position set by [ pclpst a2 : pclst a 0]-bit, the pedestal clamp timing pulse is not generated. t h is avoids mis-clamping of serration pulse input. * operation w i th ty pical video input signal * operation w i th serration pulse input signal at hsync input video signal in loacation of hsy nc (ain1/ain2/ain3) 1clock = 37nsec a fter lpf sy nc1/2/3 input hsy n c r=620 c=510pf lpf 380nsec 70m v a fter sy nc separation internal sy nc reference (syncdet ) 2+[pclpsta3: pclpst a0]-bit [clks] [pc l pw id t h 3: pc lpw i d t h 0 ]-bit c l ocks pedestal clamp timing pulse at serration pulse input a fter sy nc separation internal sy nc reference (syncdet ) pedestal clamp timing pulse a fter lpf sy nc1/2/3input serration pulse 2+[pclpsta3: pclpst a0]-bit [clks] rev.0 30 2002/01
asahi kasei [AK8850] ( 1-3 ) clamp pulse mask funct ion t o avoid mis-clamping, the syncdet signal is masked outsi de the sync signal period. t he masking period is from the rising edge of the syncdet signal to 1536 clock periods ( 1 cl ock = 37 ns ). during this period, no syncdet signal is generated ( refer to the timing diagram below ). t h is pulse mask is reset via register programming ( refer to item 1-6-5 ). input video sy ncdet clpmask 1536 clks ( 1-4 ) ex t e rnal clamp t i ming input via ex t c lp pin it is possible to input an external clamp timing pulse via the ext c lp pin by setting the inclpt mg-bit and [ fbclpt mg1 : fbclpt mg0 ]-bits of the [ clamp cont ro l regist e r ]. f o r further register settings, please refer to item ( 1-6 ) sync separat ion regist e r relat e d descript ion. ( 1-5 ) clamp t i ming pulse monit o r funct ion it is possible to monitor the internal clamp timing through the ext c lp pin only w hen no external clamp timing is used. output signals monitored on ext c lp pin are sync-t i p clamp timing pulse, pedestal clamp timing pulse and syncdet signal. t he target signal is selected by [ ext c lp 1 : ext c lp0 ]-bit of the [ clamp t i ming 1 cont rol regist e r ]. ( 1-6 ) sync-separat ion relat e d regist e r descript ion sy nc-separation and clamp pulse relat ed registers are [ input signal select regist e r ], [ clamp cont rol regist e r ], [ clamp t i ming 1 cont rol regist e r ] and [ clamp t i ming 2 cont rol regist e r ]. select sy nc-separation signal is done using the [ input signal select regist e r ]. [input signal select register] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r e s e r v e d r e s e r v e d s y n c i n 1 s y n c i n 0 i n s e l 3 i n s e l 2 i n s e l 1 i n s e l 0 default value 0 0 0 1 0 0 0 1 [ syncin 1 : syncin 0 ]-bit selects one of the sync 1 / 2 / 3 input signals to generate the clamp pulse. [sy ncin1:sy ncin0] (bit5:bit4) target video signal for sy nc separation 0 0 n o i n p u t 01 video signal input from sy nc1 pin 10 video signal input from sy nc2 pin 11 video signal input from sy nc3 pin rev.0 31 2002/01
asahi kasei [AK8850] ( 1-6-1 ) clamp t i ming pulse source set input clamp setting is done via the [ clamp cont rol regist e r ]. [clamp control register] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 u n m a s k r e s e r v e d aclamp inclptmg f b c l p t m g 1 f b c l p t m g 0 c l p l v l 1 c l p l v l 0 default value 0 0 0 0 0 0 0 0 [ inclpt mg]-bit sets the clamp ti ming pulse of the input clamp. inclptmg-bi t (bi t -4) clamp timing pulse generation 0 clamp timing pulse generated by in ternal clamp pulse generator 1 clamp timing pulse from extclp pin [ f b clpt mg1 : f b clpt mg0]-bit sets t he clamp position and the clamp source. [fbclptmg1:fbclptmg0]-bit (bi t -3:bi t -2) clamp timing pulse 00 video signal is clamped at sy nctip level w i th internal clamp timing pulse (default) 01 video signal is clamped at sy nctip leve l w i th external clamp timing pulse 10 video signal is clamped at pedestal leve l w i th internal clamp timing pulse 1 1 r e s e r v e d combinations of inclpt mg-bit, the [f bclpt m g1 : f b clpt mg0 ]-bit and input / output setting of the ext c lp pin in various modes are show n in the follow i ng table. some co mbinations are?prohibited? as show n in the table, and therefore should not be sele cted ( otherw i se internal timing has priority ). internal clamp timing monitoring is described below .. [ fbclptmg1:fbclptmg0]-bi t sy nctip clamp fbclptmg1=0 pedestal clamp fbclptmg1 =1 internal timing fbclptmg0=0 external timing fbclptmg0=1 internal timing fbclptmg0=0 external timing fbclptmg0=1 0 (internal timing) extclp = o u tput sy nctip clamp prohibit extclp = o u tput pedestal extclp = input pedestal clamp inclptmg-bit 1 (external timing) prohibit extclp =input sy nctip clamp extclp = input pedestal clamp prohibit ( 1-6-2 ) int e rnal clamp t i ming mo nit o ring funct ion via ext c lp pin it is possible to monitor the clamp timing pulse on ext c lp pin. t h is is enabled by the [ ext m on1 : ext m on0 ]-bit of the [ clamp t i ming1 cont rol regist e r ]. t he timing pulse monitor function is disabled w hen the external clamp pulse input is selected. * [ clamp t i ming 1 cont rol regist e r ] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ex t m o n 1 e x t m o n 0 sclpw i d t h 2 s c l p w i d t h 1 s c l p w i d t h 0 s c l p s t a t 2 s c l p s t a t 1 s c l p s t a t 0 default value 0 0 0 0 0 monitoring of clamp timing is possible by setti ng [ inclpt mg : fbclpt mg 1 : fbclpt mg 0 ]-bit. [inclptmg: fbclptmg1:fbclptmg0]-bit monitor w i th extclp pin note [ 0 0 0 ] p o s s i b l e sy n c t i p c l a m p [ 0 1 0 ] p o s s i b l e p e d e s t a l c l a m p rev.0 32 2002/01
asahi kasei [AK8850] monitor pulse is selected as follow s . [extmo n1:extmo n0]-bit monitor source note 00 high impedance ( unavailabl e monitoring) default 01 internal sy nctipu clamp timing pulse 10 internal pedestal clamp timing pulse 1 1 s y n c d e t p u l s e ( 1-6-3 ) sync-t i p clamp t i ming pulse set w hen using the internal sync-t i p clamp timing pulse for clam p functions, set the start pos ition and pulse w i dth of the sync-t i p clamp timing pulse using the [ clamp t i ming1 cont rol regist e r ].t his setting is valid only w hen the [ inclpt mg : fbclpt mg1 : fbclpt mg0 ]-bits are set to us e the internal clamp pulse for sync-t i p clamping ( it is invalid if external clamp pulse is used ). t o monitor the clamp pulse timing generated by the internal clamp circuit, ensure that [ ext m on1 : ext m on0 ]-bit of the [ clamp t i ming1 cont rol regist e r ] is properly set. t he slice level is adjustable by setting [ slclv 1 : slcl v 0 ]-bit of the [ clamp t i ming 2 cont rol regist e r ]. * [ clamp t i ming1 cont rol regist e r ] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ex t m o n 1 e x t m o n 0 sclpw i d t h 2 s c l p w i d t h 1 s c l p w i d t h 0 s c l p s t a t 2 s c l p s t a t 1 s c l p s t a t 0 default value 0 0 0 0 0 0 start position of the analog sync-t i p clam p timing pulse is set by [ sclpst a2 : sclpst at 0]-bit ,and the clamp pulse w i dth is adjusted using the [ sclpw i dt h3 : sclpw i dt h0 ]-bit. * w hen [ sclpst a2 : sclpst at 0 ]-bit and [ sclpw i dt h3 : sclpw i dt h0 ]-bit are valid, settings are as follow s . [inclptmg: fbclptmg1:fbclptmg0]-bit monitor w i th extclp note [000] available internal sy nctip clamp pulse [ 0 1 0 ] a v a i l a b l e i n t e r n a l pedestal clamp timing pulse [ 0 1 1 ] u n a v a i l a b l e e x t e r n a l pedestal clamp timing pulse sync-t i p clamp pulse related settings are show n below . * sync-t i p clamp pulse start position set by [ sclpst at 2 : sclpst at 0 ]-bit [sclpst at 2:sclpst at 0]-bit start position from the falling edge of sy nchronization pulse actual clamp pulse timing position 000 passed after 0-clocks (0nsec) passed after 2-clocks (74nsec) 001 passed after 2-clocks (74nsec) passed after 4-clocks (148nsec) 010 passed after 4-clocks (148nsec) passed after 6-clocks (222nsec) 011 passed after 6-clocks (222nsec) passed after 8-clocks (296nsec) 100 passed after 8-clocks (296nsec) passed after 10-clocks (370nsec) 101 passed after 10-clocks (370nsec) passed after 12-clocks (444nsec) 110 passed after 12-clocks (444nsec) passed after 14-clocks (481nsec) 111 passed after 14-clocks (518nsec) passed after 16-clocks (592nsec) [ sclpst at 2 : sclpst at 0 ]-bit is used to fine-tune the star t position w hose default value is [001], or 2 clocks (74ns). t he clamp start position is adjusted w i th the [ sclpst at 2 : sclpst at 0 ]-bit as follow s . t he actual clamping position occurs 2 clock cy cles after sy nc pulse is generated.. rev.0 33 2002/01
asahi kasei [AK8850] * sync-t i p clamp pulse w i dth set by [ sclpw i dt h2 : sclpw i dt h0 ]-bit [sclpwidt h 2: sclpwidt h0]-bit pulse w i dth 0 0 0 2 - c l o c k s ( 7 4 n s e c ) 0 0 1 4 - c l o c k s ( 1 4 8 n s e c ) 010 8-clocks (296nsec) (default) 0 1 1 1 6 - c l o c k s ( 5 9 2 u s e c ) 1 0 0 2 4 - c l o c k s ( 8 8 8 n s e c ) 1 0 1 3 2 - c l o c l s ( 1 . 1 8 u s e c ) 1 1 0 4 0 - c l o c k s ( 1 . 4 8 u s e c ) 1 1 1 4 8 - c l o c k s ( 1 . 7 8 u s e c ) sync-t i p clamp pulse w i dth is set using the [ sclpwidt h2 : sclpwidt h0 ]-bit = [010], w i th ( 8 clocks = 296 ns) as the default value. clamp pulse w i dth c an be adjusted using the [ pclpw i dt h3 : pcldw i dt h0 ]-bit as show n below . * [ clamp t i ming2 cont rol regist e r ] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 s l c l v 1 s l c l v 0 pclpw i d t h 2 p c l p w i d t h 1 p c l p w i d t h 0 p s c l p s t a t 2 p c l p s t a t 1 p c l p s t a t 0 default value 0 0 0 1 1 1 0 0 please use slclv1 : slclv0 to adjust the sync-t i p slice position. [slclv1: slclv0]-bit slice level 00 sliced at the position from about 70mv over sy nctip. 01 sliced at the position from about 140mv over sy nctip. 1 0 i n v a l i d s e t t i n g 11 sliced at the position from about 105mv over sy nctip. t he default sync-t i p clamp timing pulse generates a clam p pulse as show n in the follow i ng timing diagram. video input sy nc position (ain1/ain2/ain3) 1clock = 37nsec a fter lpf sy nc1/2/3 input hsy n c r=620 c=510pf lpf 380nsec 2 [ clks ] + 2 [ clks ] = 4 [ clks ] ( 148 [ nsec ]) sy nctip clamp timing pulse 296 [nsec] 380[nsec] + 148[nsec ] = 528[nsec] 70mv(default a fter sy nc separation internal sy nc reference (syncdet ) 824 [nsec] default sy nctip clamp t i ming rev.0 34 2002/01
asahi kasei [AK8850] ( 1-6-4 ) set t i ng of pedest al clamp t i ming pulse both the start position and pulse w i dt h of the pedestal clamp timing pulse are programmable.it is done using the [ clamp t i ming 2 cont rol regist e r ]. t h is is valid only w hen [ inclpt mg : f b clpt mg1 : f b clpt mg 0 ]-bit is set, causing the internal clamp pulse to be used for pedestal clamping ( it is invalid if an external clamp pulse is used ). t o monitor the clamp timing pulse generated by an internal clamp timing circuit, proper setting of the [ ext m on1 : ext m on0 ]-bits of the [ clamp t i mi ng1 cont rol regist e r ] is required. * [ clamp t i ming2 cont rol regist e r ] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 s l c l v 1 s l c l v 0 pclpw i d t h 2 p c l p w i d t h 1 p c l p w i d t h 0 p s c l p s t a t 2 p c l p s t a t 1 p c l p s t a t 0 default value 0 0 0 1 1 1 0 0 t he start position of the pedestal clam p timing pulse is set by [ pclpst a2 : pclpst at 0 ]-bit,and the clamp pulse w i dth is adjusted by [ pclpw i dt h3 : pclpw i dt h0 ]-bit. * w hen [ pclpst a2 : pclpst at 0 ]-bit and [ pclpw i dt h3 : pclpw i dt h0 ]-bit are valid,the setting is as follow s . [inclptmg: fbclptmg1:fbclptmg0]-bit monitoring w i th extclp [ 0 1 0 ] a v a i l a b l e i n t e r n a l pedestal clamp timing pulse [ 1 1 0 ] u n a v a i l a b l e e x t e r n a l pedestal clamp timing pulse set the start position and the pulse w i dt h of the pedestal clamp timing pulse. * pedestal clamp timing pulse start position set by [ pclpst at 2 : pclpst at 0 ]-bit [pclpstat2:pclpstat0]-bit (bi t -2:bi t -0) start position from the falling edge of sy nchronization pulse color subcarrier cy cles from the falling edge of hsy nc 000 passed after 118-clocks (4.37usec) 17cy c les 001 passed after 126-clocks (4.65usec) 18cy c les 010 passed after 132-clocks (4.88usec) 19cy c les (color burst start position of the standard ntsc video signal) 011 passed after 140-clocks (5.18usec) 20cy c les 100 passed after 148-clocks (5.49usec) 21cy c les (default) 101 passed after 156-clocks (5.77usec) 22cy c les 110 passed after 164 clocks (6.07usec) 23cy c les 111 passed after 172 clocks (6.36usec) 24cy c les [ pclpst at 2 : pclpst at 0 ]-bit is used to fine-tune the start position w h ich is set to be 2 clocks later [100 ] as default value. clamp pulse start position changes as follo w s by [ pclpst at 2 : pclpst at 0 ]-bit. * pedestal clamp pulse w i dth set by [ pclpw i dt h2 : pclpw i dt h0]-bit [pclpwidth2: pclpwidth0]-bit (bi t -6:bi t -4) pulse w i dth 0 0 0 1 6 - c l o c k s ( 5 9 2 n s e c ) 0 0 1 2 4 - c l o c k s ( 8 8 8 n s e c ) 0 1 0 2 8 - c l o c k s ( 1 . 0 4 u s e c ) 0 1 1 3 2 - c l o c k s ( 1 . 1 8 u s e c ) 1 0 0 4 0 - c l o c k s ( 1 . 4 8 u s e c ) 1 0 1 4 4 - c l o c k s ( 1 . 6 3 u s e c ) 1 1 0 4 8 - c l o c k s ( 1 . 7 8 u s e c ) 1 1 1 5 2 - c l o c k s ( 1 . 9 2 u s e c ) pedestal clamp pulse w i dth is set to its default value of [011] via the [ pclpwidt h2 : pclpwidt h0 ]-bits =( 32 clocks = 1.18 micro sec ). t he clamp pulse w i dth is adjusted using the [ pclpw i dt h3 : pclpw i dt h0 ]-bit as follow s . rev.0 35 2002/01
asahi kasei [AK8850] t he pedestal clamp timing pulse at the default state generates a clamp pulse as show n in the follow i ng timing diagram. video signal input position of hsy nc (ain1/ain2/ain3) 1clock = 37nsec a fter lpf sy nc1/2/3 input hsy n c 380nsec 70mv a fter sy nc separation internal sy nc reference (syncdet ) [pc l pst a3: pc lpst a0]-bit c l ocks [pc l pw id t h 3: pc lpw i d t h 0 ]-bit c l ocks pedestal clamp timing pulse 5.3usec 4.92usec=133[clk] ( default 5.48usec = 148 [clk] ) default v a lue is 21 cy cles 2.5usec default pedestal clamp timing ( 1-6-5 ) clamp t i ming pulse mask funct ion t he clamp timing pulse generation is masked at the default st ate to avoid mis-clamping out side the sync signal timing. t h is masking function can be disabled. * [ clamp cont rol regist e r ] set is done by u n m a s k - b i t unmask-bit f unction 0 m a s k e d d e f a u l t 1 u n - m a s k e d for ty pical use,please set unmask bit =0. rev.0 36 2002/01
asahi kasei [AK8850] ( 2 ) input signal clamp funct ion t h is function clamps the input signal to a proper level. t he circuit clamps the sync-t i p level of input signal to approximately 0.7 v. t he input signal is clamped at the position as show n below . t he clamp timing pulse is controlled by either the internal sy nc-separation circuit or by an externally -fed clamp timing pulse via ext c lp pin ( please refer to sync-t i p clamp timing pulse item ). clamp timing clamp level ( 2-1 ) input clamp control register: * input signal clamp on /off bit : aclamp-bit ( bit-3 ) aclamp function 0 clamp on (default) 1 c l a m p o f f t he input signal clamp function can be turned ?off, for ex ample, w hen dc signals are input.. set aclamp= 0 ( on ) for normal operation. ( 3 ) analog clamp funct ion t h is function clamps the input signal using analog signal processing for a higher degree of precision, enabling sync-t i p to be clamped to approximately 0.7 v by the input signal clamping. either of the sync-t i p clamp or t he pedestal clamp is selectable by t he [ clamp cont rol regist e r ]. clamp timing is controlled by a clamp pulse that is generated by an internal sy nc-separation circuit. it is also possible to control it w i th an external signal connected to the ext c lp pin. either the sync-t i p clamp or the pedestal clamp must be selected and its clamp level set by [ clplvl 1 : clplvl 0 ]-bit. if an internal clamp pulse is used, the selected clamp pul se can be output on the ext c lp pin. w hen the c signal and pb / pr component signals are input, the clamp levels of clamp2 / clamp3 ar e set to fixed values. ( 3-1 ) clamp cont rol regist e r descript ion clamp function is set by [ clamp cont rol regist e r ]. * [ clamp cont rol regist e r ] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 c l p m a s k r e s e r v e d a c l a m p inclptmg f b c l p t m g 1 f b c l p t m g 0 c l p l v l 1 c l p l v l 0 default value 0 0 0 0 0 0 0 0 [clplvl1: clplvl0]-bit (bit1:bi0) clamp level note [ 0 0 ] s y n c t i p clamped at sy nctip level. when internal clamp pulse is used, set to this mode [ 0 1 ] p e d e s t a l clamped at pedestal level for 286mv sy nc levels and analog pedes tal clamp settings, use this mode. 286mv sy nc : ntsc composite , y / c signal , betacam component [ 1 0 ] p e d e s t a l clamped at pedestal level for 300mv sy nc level and analog pedesta l clamp settings, use this mode. 300mv sy nc : 625 component, miicomponent [ 1 1 ] c l a m p o f f analog clamp function is off t he control clamp timing is done by setting the clamp pulse timing [ clpt mg 1 : clpt mg 0 ]-bit. rev.0 37 2002/01
asahi kasei [AK8850] * clamp timing is set by [ fbclpt mg 1 : fbclpt mg 0 ]-bit ( bit-3 : bit-2 ). [fbclptmg1:fbclptmg0]-bit clamp pulse 00 internal sy nctip clamp pulse 01 internal pedestal clamp pulse 10 external clamp timing pulse input from extclp pin. 1 1 r e s e r v e d * clamp timing and clamp level are summarized in the follow i ng table. internal clamp timing pulse external clamp timing pulse 286mv sy nc signal 300mv sy nc signal 286mv sy nc signal 300mv sy nc signal bit set sy nctip clamp pedestal clamp sy nctip clamp pedestal clamp sy nctip clamp pedestal clamp sy nctip clamp pedestal clamp [fbclpt m g1:fbclpt m g0]- bit 0 0 0 1 0 0 0 1 1 0 1 0 1 0 1 0 [c lplvl1:c l plvl0]- b i t 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 ( 4 ) digit al pedest al clamp funct ion t h is function clamps at the pedestal position the analog-clamped input signal by using digital signal processing. f o r details, please refer to digital portion details. rev.0 38 2002/01
asahi kasei [AK8850] 7-2-3 pga ( programmable gain amp ) a programmable gain amp ( pga ) to adjus t input signals to their proper levels. t he gain range of the pga is from 0 db to 12 db w i th the gain step of 0.1 db / step ( 127 steps ).w hen the agc function is enabled,pga1 / pga 2 / pga 3 are properly gain set by di gital control. agc function is disabled by default and the gain of each pga is independent ly set via registers. pga control register description: t o manually control the pga, the agc function is turned off by the [ cont rol 1 regist e r ]. t he agc function is disabled by default. * [ cont rol 1 regist e r ] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r c s y n c r e s e r v e d int p o l [ 1 ] int p o l [ 0 ] a g c c 1 a g c c 0 agct 1 agct 0 default value 1 0 0 0 0 0 0 0 to the agc must be disabled in order to set pga manually . t he setting is done as follow s : i.e., set [ agct 1 : agct 0 ] = [ 0,0 ]. [agct1:agct0](bit-1:bit-0) agc function [ 0 , 0 ] d i s a b l e (default) [ 0 , 1 ] t = 1 f i e l d [ 1 , 0 ] t = 7 f i e l d [ 1 , 1 ] t = 2 9 f i e l d f o r further details of agc function, pleas e refer to the agc description section. * [ pga 1 /2 /3 gain cont rol regist e r ] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved p g a 1 / 2 / 3 [ 6 ] p g a 1 / 2 / 3 [ 5 ] p g a 1 / 2 / 3 [ 4 ] p g a 1 / 2 / 3 [ 3 ] p g a 1 / 2 / 3 [ 2 ] p g a 1 / 2 / 3 [ 1 ] p g a 1 / 2 / 3 [ 0 ] default value 0 1 0 0 0 0 0 0 registers for setting the pga gain values are [ pga 1 / 2 / 3 gain cont rol regist e r ]. each pga has a corresponding register. [ pga 1 gain cont rol regist e r ] example is show n here. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r e s e r v e d p g a 1 [ 6 ] pga1[5 ] p g a 1 [ 4 ] p g a 1 [ 3 ] p g a 1 [ 2 ] p g a 1 [ 1 ] p g a 1 [ 0 ] default value 0 1 0 0 0 0 0 0 each value set by pga 1 / 2 / 3 [ 6 : 0 ]-bit uses 0.1 db / step increments. t he default gain is set to approximately 6 db ( pga 1 /2 / 3 [ 6 : 0 ]= 0x40 ). rev.0 39 2002/01
asahi kasei [AK8850] 7-2-4 clock modes t he AK8850 operates under the follow i ng 3 clock modes. (1) line-locked clock mode a high quality input signal from a signal generator or dv d can be used and the corresponding horizontal sy nc signal ( hsync ) can be extracted. a clock generated in this w a y is called line-locked clock. even if the line-locked clock mode is selected, it is possible for the chip to be fo rced into f i xed?clock mode, depending upon the input signal quality (poor or no-input signal conditions). ( 2 ) frame-locked clock mode t he vertical sy nc signal in the input signal is used to gener ate a clock w hen skew exists in the input signal, as in the case of a vcr. a clock generated in this w a y is called f r ame-locked clock. even if t he f r ame-locked clock mode is selected, there is a case to be forced to the f i xed-clo ck mode w h ich is depending on the i nput signal quality ( poor or no- input signal conditions). ( 3 ) fix e d-clock mode a clock not affected by pll control. ( 4 ) clock aut o t r ansit ion mode ( default mode ) depending on the characteristics of the i nput signal, the clock mode is automatic ally selected. w hen the auto select mode is enabled, the AK8850 automat ically shifts its clock mode from / to line-clocked mode to / from f r ame-locked mode then to f i xed-clock mode until it selects the optimum mode. since an input- signal-sy n chronized clock can be generat ed in both the line-locked clock and f r ame-locked clock modes, it u-r bt .656 compatible output is ava ilable if the input si gnal quality is good enough. in f i xed clock mode operation, the AK8850?s pll is disabled. t h is clock mode is usually selected w hen the input signal quality is poor and the auto clock mode is set by clock m ode register. in this mode, the input clock must be sy nchronized w i th the input signal so that output data remain s compatible w i th it u-r bt .656 specifications. an external vcxo clock circuit connection is show n below . t he AK8850 internally sw itches the line and the f r ame-locked loop f ilter outputs, and adds the v-i converted current and the internal current dac output together, then it outputs this value on the ivcxo pin. by connecting an external resistor to this pin, a control voltage to the external vcxo is provi ded. a voltage to control the oscillating center fr equency of the vcxo is adjustable by setting the above-mentioned current dac input code, using the pll-dac code set register ( address : 0x47 ). in this case, adjusting the external vcxo oscillating center frequency is accomplished by selecting the f i xed clock mode [ cont rol 2 regist e r ]. fl pf ll pf cl k iv cx o i n t ern al cl oc k 10 k ?
asahi kasei [AK8850] * [ clkmode1 : clkmode0 ]-bit set [clkmode1: clkmode0 ] 00 fixed clock external clock mode 0 1 l i n e - l o c k e d c l o c k line lock clock mode according to the input video signal quality , AK8850 w o rks in fixed clock mode. 1 0 f r a m e - l o c k e d c l o c k frame lock clock mode according to the input video signal quality , AK8850 w o rks in fixed clock mode. 11 auto clock mode according to the input video signal quality , clock mode is sw itched to the most suitable clock mode.(default) t he vcxo?s oscillating center frequency c ontrol voltage is adjusted by setting t he dac output current value [ pll dac set regist e r ]. in fixed clock mode operation, the vcxo oscillating frequency is fixed by the value set here. * [ pll dac set regist e r ] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p l l d a c i 7 p l l d a c i 6 p l l d a c i 5 p l l d a c i 4 p l l d a c i 3 p l l d a c i 2 p l l d a c i 1 r e s e r v e d 1 0 0 0 0 0 0 0 t he dac?s upper 7 bits are valid. adjustable dac current value ranges are as follow s . plldac[7:1] [ua] ty p . ) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 7 ( 7-2-5 ) loop f i lt er t he AK8850 requires external loop filt ers. proper loop filters should be connected for the line-locked and the f r ame-locked plls respectively . t he optim um value of the loop filter constant varies w i th the vcxo gain [ ppm / v ] characteristics. llpf (for line lock) flpf (for frame lock r1 c1 c2 llpfc ( for line lock) flpfc ( for frame loc k ) an exam ple of the loop filter constant for a 100 ppm /v vcxo is shown ( ivcxo output load resistor at 10 kohm ).t h is loop filter constant ( reference value ) is set by the [ pll cont rol regist e r ] ( sub address 0x46 ) [ lpgaut o ]-bit [lpgaut o] - bit = 0 (default) [lpgaut o]-bit = 1 r c1 c2 r c1 c2 line lock 9.1k ? ? ? ?
asahi kasei [AK8850] ( 7-2-6 ) adc t he AK8850 integrates three 27 mhz 10-bit adcs ( adc1 / a dc2 / adc3 ).each adc can be disabled by the [ pow e r save mode regist e r ]. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r e s e r v e d r e s e r v e d r e s e r v e d r e s e r v e d a d c 2 a d c 1 a d c 0 p s default value 0 0 0 0 0 0 0 0 * adc1 /2 / 3 ? bit set adc1/2/3-bit function note 0 adc1/2/3 active mode 1 adc1/2/3 sleep mode each adc can be set sleep mode individually rev.0 42 2002/01
asahi kasei [AK8850] 7-3 digit al signal processing block diagram 7-3-1 digital block details clamp1_lev[1:0] y u v demodulation 10- bitad 10- bitad composite or y [ 9:0 ] y/ c c[9:0] adaptive y c -separation multiplier multiplier a cc y u v 601 formatter pga_gain[6:0] x 3 acc lpf lpf sy nc rejection contrast brightness clk _ mode select 656 formatter & buffer y cb cr host interface c o mposi t e si g nal c c multiplexer t i ming controller & other f unction sy nc detect sy nc separation vco control (phas e error detec t ) agc control cc/vbid/wss/aspect ex traction etc. chroma pll (hue control) dfs pixel interpolator y 10- bitad component cb[9:0] component cr[9:0] v u hsy nc vsy nc field frame0 frame1 dvalid nstd nsig clk27mout halfclkout sela scl sda /reset dvdd dvss data[7:0] input_sel clamp_pulse_sel reset decimation filter 27mhz
asahi kasei [AK8850] 7-4 digit al signal processi ng funct ional specificat ion 7-4-1 decimation f ilter composite, yc, and component input signal s are sampled at 27 mhz and then are dow n- sampled to 13.5 mhz by the decimation f ilter. t he f r equency response of t he decimation f ilter is show n as follow s . -7 0 -6 0 -5 0 -4 0 -3 0 -2 0 -1 0 0 10 0. 0 1 . 0 2 . 0 3 . 0 4. 0 5 . 0 6. 0 7 . 0 8. 0 9 . 0 10. 0 1 1. 0 12. 0 13. 0 fr e q ue nc y [ m h z ] ga i n [ d b] 7-4-2 sync-separation, sync-dete ction, phase-error detection t h is detects sync-signal position of the discrete signal. t he detect ed sync signal controls the pll. 7-4-3 digit al pedest al clamp t h is sets the digitized data pedestal position 240 / 252 le vels ( 286 mv-ty pe sync / 300 mv-ty pe sync ). t h is function decreases the effect of sync level dept h variations in the video. t he contro l-time-constant and non-sensing bandw idth can be set by the [ cont rol 2 regist e r ]. f o r 286 mv-ty pe sync and 300 mv-ty pe sync details, please refer to [ t able 7-2-1-1 ] in section [ 7-2-1 input signal select o r mode ]. digital pedestal clamp control register description : * [ cont rol 2 regist e r ] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 c l k m o d e 1 c l k m o d e 0 acc1 acc0 dpcc1 dpcc0 dpct 1 dpct 0 default value 1 1 0 0 0 0 0 1 t he control-time-constant is set by the [ dpct 1 : dpct 0 ]-bit ,and the non-sensing bandw idth is set by the [ dpcc1 : dpcc0 ]-bit. [dpct 1 :dpct 0 ] pedestal clamp t i me constance 0 0 o f f 01 f a st (default) about 1.5-lines 1 0 m i d d l e about 3 . 5 - l i n e s 1 1 s l o w about 7 . 5 - l i n e s rev.0 44 2003/01
asahi kasei [AK8850] * non-sensing bandw idth of the pedestal clamp is set as follow s . [dpcc1:dpcc0] 286mv sync pedestal level 240 300mv sy nc pedestal level 252 00 default pedestal level is not 240, digital pedestal clamp function w o rks. pedestal level is not 252, digital pedestal clamp function w o rks. 01 non-sensing bandw idth : + / - 1lsb pedestal level is not in the range of 238 - 241, digital pedestal clamp function w o rks non-sensing bandw idth : + / - 1lsb pedestal level is not in the range of 250 - 253, digital pedestal clamp function w o rks 10 non-sensing bandw idth : + / - 2lsb pedestal level is not in the range of 236 - 243, digital pedestal clamp function w o rks non-sensing bandw idth : + / - 2lsb pedestal level is not in the range of 248 - 255, digital pedestal clamp function w o rks 11 non-sensing bandw idth : + / - 3lsb pedestal level is not in the range of 232 - 247, digital pedestal clamp function w o rks non-sensing bandw idth : + / - 3lsb pedestal level is not in the range of 244 - 259, digital pedestal clamp function w o rks 7-4-4 agc ( automatic gain control ) t h is function sets the pga gain so that input level is properly set. t he pga gain is calculated so that the sync level is equal to 40 ire / 300 mv ( 286 mv-ty pe sy nc / 300 mv-ty pe sy nc ) and its value is set to pga ( classification of 286 mv-ty pe sy nc and 300 mv-ty pe sy nc is listed in t able 7-2-1-1 ). gain-calculation and gain-set are performed during the vbi interval of each f i eld. t he agc time constant is programmabl e in 3 steps using the [ cont rol 1 re gist e r ]. t he pga gain is derived from the sync level information only . agc is performed only on the composite signal and the y portion of the yc input and component input signals. auto gain is not performanced on the c-signal or pb / pr signals. it is assumed that correction of the c- signal is done using the acc of the digita l portion. correction of the component pb /pr signals should be manually done using t he color saturation control function. w hen the agc function is disabled by the [ cont rol 1 regist e r ], the gain of each channel can be manually set via the [ pga1 / pga 2 / pga 3 gain cont rol regist e r ]. agc control register description: agc is controlled by the [ cont rol 1 regist e r ]. * [ cont rol 1 regist e r ] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r c s y n c r e s e rv e d i n tpol[ 1 ] i n tpol[ 0 ] a g c c 1 a g c c 0 a g c t 1 a g c t 0 default value 1 0 0 0 0 0 0 0 agc set is defined as follow s . enable / disable and the t i me-constant ( t ) of the agc are set . [agct1:agct0](bit-1:bit-0) agc function [ 0 , 0 ] d i s a b l e ( d e f a u l t ) [ 0 , 1 ] t = 1 f i e l d [ 1 , 0 ] t = 7 f i e l d [ 1 , 1 ] t = 2 9 f i e l d t he AK8850 sets the pga value so that the sync-t i p level is equal to 40 ire / 300 mv ( 286 mv-ty pe sy nc / 300 mv-ty pe sy nc ) w h ile the agc is enabled. t he 286 mv-ty pe sy nc here means nt sc composite, nt sc yc input and betacam component signals, w h ile the 300 mv-ty pe sy nc means 625 com ponent and mii component signals. 40 ire / 300 mv ( 286 mv-ty pe sy nc / 300 mv-ty pe sy nc ) are equivalent to 240 / 252 ( 10-bit ) in digital code. as the sync-t i p is set to 16 ( 10-bit ), sy nc sizes ar e equivalent to 224 / 236 ( 10-bit ) respectively . sampled digital code sy nc level 286mv sy nc 2 4 0 2 2 4 300mv sy nc 2 5 2 2 3 6 w h ile the agc is enabled, manual gain adj ustment is not possible by the pg a1 / pga2 / pga3 gain cont rol registers ( agc has higher priori ty than manual gain adjustments ). rev.0 45 2003/01
asahi kasei [AK8850] it is also possible to program the non-sensing bandw idth of the agc by [ agcc1 : agcc0 ]-bit of the [ cont rol 1 regist e r ]. [agcc1:agcc0](bit-3:bit-2) 286mv sy nc 300mv sy nc non-sensing bandw idth [0,0] sy nc level is not 224, agc function w o rks. sy nc level is not 236, agc function w o rks. no non-sensing bandw idth [0,1] sy nc level is not in the range of 222 - 225, agc function w o rks. sy nc level is not in the range of 234 - 237, agc function w o rks. 1-bit non-sensing bandw idth [1,0] sy nc level is not in the range of 220 - 227, agc function w o rks. sy nc level is not in the range of 232 - 239, agc function w o rks. 2-bit non-sensing bandw idth [1,1] sy nc level is not in the range of 218 - 229, agc function w o rks. sy nc level is not in the range of 230 - 241, agc function w o rks. 3-bit non-sensing bandw idth same gain as for the y signal input case is multiplied to the c-signal in y / c input and the pb / pr signals in component signal input. t he gain constant value set for the ag c does not affect to any of the [ pga1 / pga2 / pga3 gain cont rol regist e r ], regardless of input sources. 7-4-5 y / c separat ion t he y / c separation function separates the composite video input signal into lum inance ( y ) and chroma signals ( c ). t h ree register-selectable y / c separat ion methods are available: primary y/ c separation ( band pass f ilter ), t w o dimensional y/c separation ( 3-line comb f ilt er ) and an adaptive y/ c separation f ilter. f o r y/c separation, the input data is converted ccir601 co mpatible formats and it is output as a y signal w hen the black & w h ite mode is selected, during the vbi interval set by [ vbil4 : vbi l0 ]-bit of the [ vert i cal blanking lengt h regist e r ]. t he output cb/cr signal is at 0x80, or black level.t he resulting output on the AK8850 is selected by vbidec-bit of the [ vert i cal blanking lengt h re gist e r ]. black level output ( y= 0x16,cb/cr= 0x80) at vbidec-bit = 0 and black & w h it e output at vbidec-bit= 1. t he y/ c separation function is enabled only w hen a composite signal is input. y/c separation control register description : t he y/c separation is controlled by the [ y/c separat ion cont rol regist e r ]. * [ y/c separat ion cont rol regist e r ] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r e s e r v e d r e s e r v e d r e s e r v e d r e s e r v e d c b p f s 1 c b p f s 0 y c s e p 1 y c s e p 0 default 0 0 0 0 0 1 1 0 t he y/c separation mode is set as follow s . [y csep1:y csep0] (bi t -1:bi t -0) y c -separation mode 00 3-line 2-d y c -separation 01 1-line bpf y c -separation 10 adaptive 3-line 2-d y c -separation (default) 1 1 r e s e r v e d 3 ty pes of the color band?limiting filter s are selectable w h ich are used for y/ c separation. use the[ y/c separat ion cont rol1 regist e r ] to select. t he band limiting f ilters are applicable for all y/c separation modes ( in black & w h ite mode, filter selection becomes invalid since the y/c separat ion function is disabled ). [cbpfs1:cbpfs0] (bi t -3:bi t -2) chroma bandw idth filter characteristic -3db 0 0 o f f o f f 0 1 w i d e ( d e f a u l t ) + / - 1 m h z 1 0 m i d d l e + / - 7 5 0 k h z 1 1 n a r r o w + / - 5 0 0 k h z rev.0 46 2003/01
asahi kasei [AK8850] 7-4-6 acc ( auto color control ) t h is function adjusts the color burst leve l of the c-signal input to its appropriate level, w h ich is 40 ire ( w i th nt sc composite ,y/c input ). t he adjustable range is from ?12 db to + 12 db. t he acc processing can be turned on or off by the [ cont rol 2 regist e r ]. its function is valid for co mposite and y/c inputs ( inva lid for component input ). acc control register description : acc is controlled by [ cont rol 2 regist e r ]. * [ cont rol 2 regist e r ] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 c l k m o d e 1 c l k m o d e 0 acc1 acc0 dpcc1 dpcc0 dpct 1 dpct 0 default value 1 1 0 0 0 0 0 1 enable/disable and the constant ( t ) of the acc are set as follow s . [acc1:acc0](bit-5:bit-4) acc function [ 0 , 0 ] d i s a b l e ( d e f a u l t ) [ 0 , 1 ] t = 2 - f i e l d [ 1 , 0 ] t = 8 - f i e l d [ 1 , 1 ] t = 3 0 - f i e l d t he acc and the color saturati on adjustments function independently . rev.0 47 2003/01
asahi kasei [AK8850] 7-4-7 color killer t he signal quality of the chroma signal is evaluated from the color burst level of i nput signal. if this level is low e r than a target level, the chroma signal decoding process is not performed. w hen the standard 40 ir e color burst input signal level becomes low e r than the pre-set value (presettable range is from ?17 db to ? ( in finite ),-20 db at default ), the color killer function is activated.t he cb/c r output signal is fixed to 0x80. when the color killer is activa ted, the c-data output is 0x 80, (black & white mode). sinc e the color killer function checks the color burst signal, it is disabled w hen the component signal is selected. operating range of the color k iller can be set from ?17 db to ? ( infinite ). it can be turned on or off by the [ color killer cont rol regist e r ]. w hen the color killer process is executed, the chroma signal output becomes black level ( 0x80 ) w h ich is a similar level in the black & w h ite mode. how e ver, si nce the c-signal is subtra cted from the composite si gnal by the y/c separation block, the output result differs from the black & w h ite mode. color killer control register description : color killer function is controlled by the [color killer cont rol regist e r ]. * [ color killer cont rol regist e r ] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 c l _ k i l l r e s e r v e d c k l v l 5 cklv l 4 c k l v l 3 c k l v l 2 c k l v l 1 c k l v l 0 default value 1 0 1 0 1 1 0 1 * t u rning on and off of the color killer function is set by cl-kill-bit ( bit-0 ) cl_kill-bit (bit-7) color killer 0 o f f (disable) 1 on (enable) default * t u rning on and off of the color killer function is set by cl-kill-bit ( bit-0 ) t he color killer level setting is given in the follow i ng equation: on / off decision level of the color killer is made by che cking the u level after de-modulating the color burst signal. a proper input signal gives the u-signal a leve l of 112. a decision is made w i thin the device by multiply ing by 4 the u-signal after de-modulating the input signal. t he register set value [ cklvl5 :cklvl0 ] is given as: [ cklvl5 : cklvl0 ]= 10 exp( clk/20 ) *448 w here ckl [ db ] is the level to enable color killer. in reverse, the color killer enable level is ca lculated from the register set value as : input u level = 20 *log ( [ cklvl5 : cklvl0 ] / 448 ) i.e., w hen a low e r-than-the input u level signal is input, the color killer is activated. u-signal level after demodulation color killer level (max63) set to 63(max), w hen the calculated value w h ich is 4 times the demodulated u-signal is less than 63, color killer is active. 112 rev.0 48 2003/01
asahi kasei [AK8850] 7-4-8 black & whit e mode black & w h ite mode outputs all input signals as luminance (y) only . in this mode, the c- signal output becomes 0 level (output code 0x80) and y/c separ ation function is turned off ( black & w h ite mode ). if y/c and component signals are input, the chroma signal to be out put is fixed to 0x80. t he black & w h ite mode is user programmable and it is turned on and off by the [ input video st andard regist e r ]. black & w h ite mode control register description: black & w h ite mode is controlled by the [ input video st andard regist e r ] * [ input video st andard regist e r ] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r e s e r v e d nent b / w set u p v s 3 v s 2 v s 1 v s 0 default value 0 0 0 0 0 0 0 0 * on / of f of black & w h ite mode functi on is controlled by b/w - bit ( bit-5 ) b/w - bi t (bi t -5) b/w mode set 0 off (color video signal : default) 1 on (b/w video signal * output status in black & w h ite mode ( at b/w - bit = 1 ). output data y singal out level converted value to rec.601 level. cb/cr signal out fixed value at 0x80 above output status is applicable for nt sc ( composite y/c ) and 525 & 625 component signals. 7-4-9 pict ure adjust ing funct ion t he AK8850 has picture quality adjusti ng functions w h ich include contrast, brightness, color saturation and hue adjustments. ( 1 ) cont rast t he contrast adjustment is made by mu ltiply ing the luminance signal ( y ) by the gain factor w h ich is set by the [ cont rast cont rol regist e r ]. t he contrast adjustment is made w i thin the range of 0 ~ 2 ( 1/ 255 step ). t hese arithmetic operations ar eperformed on 10-bit data. w hen the result exc eeds the specified range, it is clipped to 1023 ( upper limit ) or to 0 ( low e r limit ). contrast contrast control register : * [ cont rast cont rol regist e r ] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cont 7 c o n t 6 c o n t 5 c o n t 4 cont 3 c o n t 2 c o n t 1 cont 0 default value 1 0 0 0 0 0 0 0 sets a multiply ing factor over the lumi nance signal. adjustable range is from 0 ~ 2 in 0.008 fraction per step. default value is 0x80. rev.0 49 2003/01
asahi kasei [AK8850] ( 2 ) bright n ess brightness adjustment is accomplished by adding an offset factor to the luminance signal w h ich is set by the [ bright n ess cont rol regist e r ]. t he adjustable range is +/- 200 ( 255 steps ). ar ithmetic operations are performed on the 10-bit data. w hen the resu lt exceeds the specified range,it is clipped to 1023 ( upper limit ) or to 0 ( low e r limit ). brightness brightness control register : * [ bright n ess cont rol regist e r ] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b r 7 b r 6 b r 5 b r 4 b r 3 b r 2 b r 1 b r 0 default value 0 0 0 0 0 0 0 0 increases the value of the luminance signal. arithmetic operations are done on the 10-bit data and adjustable range is from ? 128 to + 127 w i th 1 fraction per step. t he adjustable value per step of the it u-r bt .601 compatible output is show n in the table below . t he regist er is expressed in 2?s complement form and its default value is 0x00. * adjustable value per each step input v i deo signal add v a lue (rounding) note 286mv sy nc w i thout setup 1 [br7:br0]*100/255 ntsc composite/y c /bet acam 286mv sy nc (w ith setup) 1 [br7:br0]*108/255 ntsc composite/y c /bet acam 300mv sy nc (w ithout setup) 1 [br7:br0]*102/255 mii / ebu-n10 300mv sy nc ( w i th setup ) 1 [br7:br0]*1 1 1/255 mii ( 3 ) hue cont rol hue adjustment is made by rotating the chroma signal by a predetermined angle w h ich is set by the [ hue cont rol regist e r ]. hue adjustment ranges from ? 90 degrees to + 90 degrees ( 1/255 step ). hue control is valid only w hen either a composite ory/c signals are input. hue cb c cr cb hue control register : * [ hue cont rol regist e r ] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 h u e 7 h u e 6 h u e 5 h u e 4 h u e 3 h u e 2 h u e 1 h u e 0 default value 0 0 0 0 0 0 0 0 sets the rotation angle of hue. adjustable range is + / - 90 degrees w i th 0.7 degree hue rotation per step. default value is the un-adjusted 0x00. t he value is in 2?s complement format. t he hue control is valid only w hen the composite or y/c signals are input ( it is di sabled for component input ). ntsc(525 sy stem) 625 sy stem component composite y/ c betacam mii component this register is functioned this register is disable this r egister is disable rev.0 50 2003/01
asahi kasei [AK8850] ( 4 ) color sat urat ion color saturation adjustment is made by multiply ing the ch roma signal w i th a gain factor w h ich is set by the [ sat urat ion cont rol regist e r ]. t he color saturation is adj ustable range is from ? ( infinite ) to + 6 db ( 1/ 255 step ). arithmetic oper ations are performed on the 10-bi t data. w hen the result exceeds the specified range, it is clipped to 1023 ( upper limit ) or to 0 ( low e r limit ). chrominace signal chrominace signal scaling saturation cr cr cb cb saturation control register : * [ sat urat ion cont rol regist e r ] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sat 7 s a t 6 s a t 5 s a t 4 s a t 3 s a t 2 s a t 1 s a t 0 default value 1 0 0 0 0 0 0 0 sets the chroma signal multiply ing factor. t he adjustable range is from ? ( infinite ) to + 6 db ( 0 ~ 2 ) w i th 0.008 fraction per step. default value is 0x80. rev.0 51 2003/01
asahi kasei [AK8850] 7-4-10 vert i cal blanking int e rval t h is section describes setting the vertical blanking interval (vbi ) and to set tasks to be performed during this interval. t he vertical blanking interval is set by [ vbil4 : vbil0 ]-bit of the [ vert i cal blanking lengt h regist e r ].( hereafter,vbi period means an in terval defined by [ vbil4 : vbil0 ]-bit ). default value is 0x14 ( 20 lines ). f o r normal operation, it is recommended to set the vbi interval to be more than 9 / 7 ( 525 line sy stem / 625 line sy stem ). t he v-bit transition point of the vi deo t i ming reference code can be altered by the t r svsel-bit of the [ vert i cal blanking lengt h regist e r ]. t r svsel-bit selects ei ther of the it u-r bt . 656 or smpt e 125m standards compatibility . t he relationship betw een t r svsel-bit and the video t i ming reference code v-bit is show n in the table below . t r svsel-bit standard 0 i t u - r bt . 6 5 6 1 s m p t e 1 2 5 m during the vbi period, the black level ( y = 0x10,cb/cr= 0x80 ) is output by default. by setting the vbidec-bit of the [ vert i cal blanking le ngt h regist e r ] to [1], the y/c separation function on those lines w h ich are specified during vbi interval is turned off and input signal is directly output as a y signal. t he set up-bit of the [ input video st andard regist e r ] bec omes invalid during vbi period ( no setup process is executed ). t u rning the setup process on /off on the latter half of a scan li ne line ( 0.5 h ) can be controll ed by the half su-bit w h ich is applied only to the first line of the second f i eld of active video. vbid control register description : * [ vert i cal blanking lengt h regist e r ] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v b i d e c t r s v s e l h a l f s u v b i l 4 v b i l 3 v b i l 2 v b i l 1 v b i l 0 default value 0 0 0 1 0 1 0 0 t he vbi period is set by [ vbil4 : vbil0 ]-bit. nt sc defaul t values and ty pical setups of 625 component signals are show n in the table below . 525 sy stem 625 sy stem component composite y/ c betacam mii component [vbil4:vbil0]-bit 0x14 default (20-decimal) 0x18 (24-decimal) vbi-line line1 ~ line20 line263.5 ~ line283.5 (from 430th pixedl of line-263 to 429th pixel of line-283) line623.5 ~ line625 line1 ~ line22.5 line311 ~ line335 t he vbi start line period fo r 625 component video is line 624. t he vbi period of f i eld ?2 is given as : f o r 525 sy stem, from 264 ( fixed value ) to ( set-value ) + 245. f o r 625 sy stem,from 311 ( fixed value ) to ( set value ) + 311. t r svsel-bit is the control bit that specif ies the v-bit in the rec. 656 eav/sav code. t h is bit is set by [ vbil4 : vbil0 ] and is not affected by vbi period as show n below . * < v-bit value in rec.656 t r s and the line relationship > ntsc(525 sy stem) composite/y c /component(mii,betacam) 625 sy stem component (ebu n10) v-bit trsvsel=0 trsvsel=1 trsvsel=0 trsvsel=1 v-bit = 0 line10 ~ line263 line273 ~ line525 line20 ~ line263 line283 ~ line525 line23 ~ line310 line336 ~ line623 v-bit = 1 line1 ~ line9 line264 ~ line272 line1 ~ line19 line264 ~ line282 line1 ~ line22 line311 ~ line335 line624 ~ line625 note) t r svsel-bit setting is as show n above. it is not affected by [ vbil4 : vbil0 ]-bit. t r svsel-bit setting is show n above for all modes of 525/625 sy stems. rev.0 52 2003/01
asahi kasei [AK8850] vbidec-bit is the control bit that specif ies the device operation during the period is assigned by vbi [4 : 0]-bit. t he output code is determined by the vbi period , vbidec-bit, half su-bit and set up-bit of the [ input video st andard regist e r ]. w hen half su-bit = 1, the set up processing is exec uted on the latter half 0.5 h time of the first line in the second f i eld. output status is show n in the follow i ng table. nt sc (525 sy stem) vbi dec-bit = 0 vbi dec-bit = 1 halfsu-bit = 0 halfsu-bit =1 halfsu-bit =0 halfsu-bit =1 line-1 - line-9 y = 0x 10 c = 0x 80
asahi kasei [AK8850] rev.0 54 2003/01 (1) vbidec-bit = 0 / halfsu-bit = 0 / setup-bit = 0 n o r m al decode pr ocess n o setup pr ocess vbilength [vbil4:vbil0] 524 525 1 2 3 4 5 6 7 8 9 10 11 263 264 265 266 267 268 269 270 271 272 273 y = 0x 10 cb/cr=0x 80 vbilength [vbil4:vbil0] y = input v i deo cb/cr=0x 80 (4) vbidec-bit = 1 / halfsu-bit = 1 / setup-bit = 0 (vbidec-bit = 1 / halfsu-bit = 0 / setup-bit = 0 ) n o r m al decode pr ocess n o setup pr ocess n o r m al decode pr ocess n o setup pr ocess y = 0x 10 cb/cr=0x 80 vbilength [vbil4:vbil0] n o r m al decode pr ocess n o setup pr ocess y = input v i deo cb/cr=0x 80 524 525 1 2 3 4 5 6 7 8 9 10 11 263 264 265 266 267 268 269 270 271 272 273 y = 0x 10 cb/cr=0x 80 vbilength [vbil4:vbil0] y = 0x 10 cb/cr=0x 80 n o r m al decode pr ocess n o setup pr ocess y = 0x 10 cb/cr=0x 80 y = 0x 10 cb/cr=0x 80 n o r m al decode pr ocess no setup process 524 525 1 2 3 4 5 6 7 8 9 10 11 263 264 265 266 267 268 269 270 271 272 273 y = 0x 10 cb/cr=0x 80 vbilength [vbil4:vbil0] y = input v i deo cb/cr=0x 80 vbidec-bit = 1 / halfsu-bit = 0 / setup-bit = n o r m al decode pr ocess n o setup pr ocess y = 0x 10 cb/cr=0x 80 vbilength [vbil4:vbil0] y = input v i deo cb/cr=0x 80 n o r m al decode pr ocess no setup process n o r m al decode pr ocess no setup process 524 525 1 2 3 4 5 6 7 8 9 10 11 263 264 265 266 267 268 269 270 271 272 273 y = 0x 10 cb/cr=0x 80 vbilength [vbil4:vbil0] y = 0x 10 cb/cr=0x 80 (3) vbidec-bit = 0 / halfsu-bit = 1 / setup-bit = 0 (vbidec-bit = 0 / halfsu-bit = 0 / setup-bit = 0) n o r m al decode pr ocess no setu p p rocess y = 0x 10 cb/cr=0x 80 vbilength [vbil4:vbil0] y = 0x 10 cb/cr=0x 80 n o r m al decode pr ocess no setup process n o r m al decode pr ocess no setup process (2) 0 524 525 1 2 3 4 5 6 7 8 9 1 0 1 1 y = 0x 10 cb/ c r = 0x 80 n o r m al decode pr ocess no setu p p rocess y = 0x 10 cb/ c r = 0x 80 vbilength [vbil4:vbil0] (5) vbidec-bit = 0 / halfsu-bit = 0 / setup-bit = 1 n o r m al decode pr ocess setup pr ocess ( - 7 .5%)
asahi kasei [AK8850] y = input v i deo cb/ c r =0x 80 y = input v i deo cb/cr=0x 80 * 625 sy stem vbidec-bit = 0 vbidec-bit = 1 rev.0 55 2003/01
asahi kasei [AK8850] l i ne-623. 5 (from 429th pix e l of l i ne-623) - li n e -5 y = 0x10 c = 0x80
asahi kasei [AK8850] 7-4-11 closed capt ion/closed capt ion ext e nded dat a /vbid ( cgms )/wss it is possible to request decoding of closed caption, closed caption extended data, vbid and w ss signals by programming the [ request vbi informat ion regist e r ]. t he [ st at us 2 regist e r ] tells a host that data is detected and idecoding has been co mpleted for a given decode request. decoded data are w r itten into the [ closed capt ion 1. 2 regist e r ], [ vbid 1.2 regist e r ], [ w ss 1 regist e r ] and [ wss 2 & aspect dat a regist e r ] respectively . t he closed caption data, closed caption extended data , vbid and w ss data are encoded on each specified line respectively as listed below . closed caption : nt sc specified line 21 st line closed caption extended data : nt sc specified line 284 th line vbid ( cgms data ) : 525 sy stem specified line 20 th line / 238 th line 625 sy stem specified line 20 th line / 338 th line w ss ( 625 sy stem only ) : 625 sy stem specified line 23 rd line vbi information request register : * [ request vbi info regist e r ] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r e s e r v e d r e s e r v e d r e s e r v e d w s s r q v b i d r q ext r q c c r q aspectrq default value 0 0 0 0 0 0 0 0 * [ st at us 2 regist e r ] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 a p s 1 a p s 0 r e s e r v e d w s s v b i d ex t c c aspect * read ?out line number of the vbi in formation for each mode is as follow s . ntsc(525 sy stem) 625 sy stem component composite y/ c betacam mii component closed caption line 21 line 22 extended data line 284 line 335 vbid line 20/line 283 line 20/line 333 wss line 23 rev.0 57 2003/01
asahi kasei [AK8850] a procedure to read out each data is des c ribed here. [ r eq u e st vbi in f o reg i ster] xxrq- bit = 1 ( d ecode request) start [status 2 regsiter] read ( c heck decode status bit) i f xx- bit = 1 no if closed caption, then ccrq-bit if vbid, th en vbidrq-b it if wss, then wssrq-bit if closed caption, then cc-bit if vbid, th en vbid-b it if wss, then wss-bit yes read data register i f closed caption, then[c losed caption 1 2 register ] if vbid, th en [ v bid 1 2 reg i ster] if wss, then [ v bid 1 register][ wss 2 & aspect data register] read operat ion of cl osed capt ion dat a : t o read closed-caption data, w r ite ?1? to the ccrq-bit. t he AK8850 w ill enter a w a it state for the closed caption data decoding. upon receipt of the data, it is decoded and w hen decoding is complet ed, ?1? is sent back to cc-bit of the [ st at us 2 regist e r ]. t he cc-bit is usually at ?1? right after a reset ( it becomes ?0? by w r iting ?1? at ccrq-bit ). t he decoded data is w r itten into the [ closed capt ion 1.2 regist e r ] as show n. data in the [ closed capt ion 1.2 regist e r ] is remains in this r egister until it is over-w ritten. * [ closed capt ion 1 regist e r ] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 c c 7 c c 6 c c 5 c c 4 c c 3 c c 2 c c 1 c c 0 * [ closed capt ion 2 regist e r ] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 c c 1 5 c c 1 4 c c 1 3 c c 1 2 c c 1 1 c c 1 0 c c 9 c c 8 read operat ion of closed capt ion ex t e nded dat a : w r ite ?1? at ext r q-bit, w h ich places the AK8850 into a w a it state w h ile extended data decoding occurs. t he received data is decoded and after the decoding is comp leted,?1? is sent back to ext - bit of the [ st at us 2 regist e r ]. ext - bit is usually at ?1? right after the reset ( it becomes ?0? by w r iting ?1? at ext r q-bit ). t hen the decoded data is w r itten into the [ ext e nded dat a 1.2 regist e r ] as show n. data in the [ ext e nded dat a 1.2 regist e r ] remains in this register it is over-w ritten. * [ ext e nded dat a 1 regist e r ] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ex t 7 e x t 6 e x t 5 e x t 4 e x t 3 e x t 2 e x t 1 ex t 0 * [ ext e nded dat a 2 regist e r ] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ext 1 5 e x t 1 4 e x t 1 3 e x t 1 2 ex t 1 1 e x t 1 0 ex t 9 ex t 8 rev.0 58 2003/01
asahi kasei [AK8850] read operat ion of vbid dat a t o read the vbid data, w r ite ?1? to the vbidrq-bit. t he AK8850 is put into a w a it state w h ile vbid data decodes. received w ss data is decodecd and after the decoding is comple te, ?1? is sent back to vbid-bit of the [ st at us 2 regist e r ]. t he vbid-bit is usually at ?1? after a rese t ( it becomes ?0? by w r iting ?1? at vbidrq-bit ). t he decoded 13-bit data is then w r itten into the [ vbid 1.2 regist e r ] as show n. data in the [ vbid 1.2 regist e r ] is remains until it is over-w ritten. * [ vbid 1 regist e r ] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v b i d 7 v b i d 8 v b i d 9 v b i d 1 0 v b i d 1 1 v b i d 1 2 v b i d 1 3 v b i d 1 4 * [ vbid 2 regist e r ] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r e s e r v e d r e s e r v e d v b i d 1 vbid2 v b i d 3 v b i d 4 v b i d 5 v b i d 6 read operat ion of wss dat a t o read w ss data, w r ite ?1? to the w ssrq-bit, t he AK8850 is placed into a w a it stat e w h ile the w ss data decodes. received w ss data is decoded and after the decoding is comple te, ?1? is sent back to w ss-bit of the [ st at us 2 regist e r ].wss-bit is usually at ?1? right after the rese t ( it becomes ?0? by w r iting ?1? at w ssrq-bit ). t hen the decoded data is w r itten into the [ wss 1 regist e r ] and [ wss 2 & aspect dat a regist e r ] as show n. data in the [ wss 1 regist e r ] and [ wss 2 & aspect dat a regist e r ] is remains until it is over-w ritten. * [ wss 1 regist e r ] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 g 2 - 7 g 2 - 6 g 2 - 5 g 2 - 4 g 1 - 3 g 1 - 2 g 1 - 1 g 1 - 0 * [ wss 2 & aspect dat a regist e r] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 aspect r e s e r v e d g 4 - 1 3 g 4 - 1 2 g 4 - 1 1 g 3 - 1 0 g 3 - 9 g 3 - 8 7-4-12 video aspect signal t h is command detects the video aspect signal ( refer to t he follow i ng diagram ) that is superimposed on line 16 and line 279 of the composite signal. t he aspect signal detection is performed by making a decode request w h ich is set by the [ request vbi info regist e r ]. after the decoding is completed, a dec ode complete notification is generated. t he decode data is w r itten into the aspect-bit of the [ wss 2 & aspect dat a regist e r ].a spect-bit data remains until it is over-w ritten. video aspect signal outline input signal : composite signal only ( at nt sc / yc input only ) line : 16 line and 279 line th th level : 70 + / - 25 ire rising edge point : 12.5 + / - 3.2 microsec from hsync rising edge ( at 50 % point ) falling edge point : 58.9 + / - 3.2 microsec from hsync falling edge ( at 50 % point) aspect bit : w i de at ?1? n o r m a l a t ? 0 ? 50% 50% 50% 70+/-25 ire 12.5+ /- 3.2usec 58.9+ /- 3.2usec rev.0 59 2003/01
asahi kasei [AK8850] video aspect related registers : * [ request vbi info regist e r ] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 0 r e s e r v e d r e s e r v e d r e s e r v e d w s s r q v b i d r q ext r q c c r q aspectrq default value 0 0 0 0 0 0 0 0 bit 1 * [ st at us 2 regist e r ] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 a p s 1 a p s 0 r e s e r v e d w s s v b i d ex t c c aspect a decoding request of the video aspect si gnal, superimposed on the input signal is done by w r iting ?1? to the aspect r q-bit of the [ request vbi info regist e r ]. t he AK8850 is put into a w a it state for data decoding. a decode complete signal is sent back to the [ st at us 2 regist e r ]. t he decoded data is w r itten into the [ w ss 2 & aspect dat a regist e r ]. * [ wss 2 & aspect dat a regist e r ] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 aspect r e s e r v e d g 4 - 1 3 g 4 - 1 2 g 4 - 1 1 g 3 - 1 0 g 3 - 9 g 3 - 8 aspect-bit = 0 : normal signal aspect-bit = 1 : w i de signal a video aspect decode request signal should be made only w hen nt sc composite or y/c signals are input. if a decoding request is made w i th the 525 component input, decoding is actually done as in the composite signal input case. in this case no video aspect signal exists in the si gnal and resulting data is meaningless. if a decoding request is made w i th the 625 component input, it is ignored and the request bit is kept at ?1? ). 7-4-14 digit al pix e l int e rpolat or a digital pixel interpolator is equipped in order to align pixels in the vertical direction. on / of f / aut o modes of the interpolator is selectable by the [ cont rol 1 regist e r ] se tting. if the auto mode is sele cted, the on / of f state of the interpolator is automatically se t by the clock mode used as follow s . line-locked mode : of f f r ame-locked mode : on external clock mode : on pixel interpolator related registers : * [ cont rol 1 regist e r ] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r c s y n c r e s e r v e d int p o l 1 int p o l 0 a g c c 1 a g c c 0 agct 1 agct 0 default value 1 0 0 0 0 0 0 0 * int o l1 : int o l0-bit set intpol1:intpol0 pixel interpolator 0 0 a u t o 0 1 o n 1 0 o f f 1 1 r e s e r v e d in auto mode, on / of f states of the in terpolator are selected by the clock mode used. t he interpolator mode selection is not affected by the ty pes of input signal s ( same for 525 line and 625 line sy stems ). rev.0 60 2003/01
asahi kasei [AK8850] 7-4-15 non-signal input det e ct ion t he AK8850 detects non-signal input conditi ons and, w hen detected, outputs a black level signal ( y= 0x10,cb/cr= 0x80 ). t he non-signal input condition is detected by checking for t he ex istence of the vsync si gnal. in order to have higher margin against non-standard signal inputs, the non-signal detection is made only w hen the vsync is not detected tw o or more consecutive times. t he result is output via the nsig output pin. output state: nsig= 1 ( non-signal input ) nsig= 0 ( valid input signal ) 7-4-16 st andard signal det e ct ion t he AK8850 has a standard signal detecti on function. w hen a non-standard input si gnal is detected, the nst d output pin changes to ? high ?. t he nst d output becomes ? low ? (st andard signal input ) w hen either ( a ) or ( b ) conditions below are met. ( a ) w i th component input ( 525 / 625 ), the frame configuration dur ing the past 2 frames is made w i th odd / even or e v e n / o d d s e q u e n c e . ( b ) w i th composite input ( including y/ c input ), the sch phase is w i thin + / - 67.5 degrees and the f r am e configuration is made w i t h o d d / e v e n o r e v e n / o d d s e q u e n c e . 7-4-17 out p ut f o rmat ( 601 f o rmat t e r ) t he AK8850 outputs the decoded data in it u-r bt .601 compatible format ( y/cb/cr 4:2: 2 ). t he min. and max. values of the output code are selectabl e by 601limit - bit of the [ out p ut f o rmat regist e r ]. at 601limit - bit = 0 y : 1 ~ 254 cb/cr : 1 ~ 254 at 601limit - bit = 1 y : 16 ~ 235 cb / cr : 16~ 240 output f o rmat related register : bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 a c t s t a [ 2 ] a c t s t a [ 1 ] a c t s t a [ 0 ] y cdelay [ 2 ] y cdelay [ 1 ] y cdelay [ 0 ] 6 0 1 l i m i t e r r h n d default value 0 0 0 0 0 0 0 0 rev.0 61 2003/01
asahi kasei [AK8850] 7-4-18 set up enabling and disabling set up is selected by the [ in put video st andard regist e r ]. w hen the set up-bit is ?1?, internal signal processing is performed, assuming that t he set up signal is input. t h is signal is processed outside of the vbi period. t he vbi period is set by the [ vert i cal blanking lengt h regist e r ]. signal set register w i th set up f eatures : w hen the input signal contains a set up command, set [ set up ]-bit of the [ input video st andard regist e r ] to ?1?. * input video standard register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserv e d n e n t b/w s e t u p v s 3 v s 2 v s 1 v s 0 default value 0 0 0 0 0 0 0 0 * set up-bit set setup-bit setup note 0 w i t h o u t s e t u p 1 w i t h s e t u p setup process should be done exclusive the term of vbi interval. setting is not affected by input signal ty pes ( composite, yc and component signals ). w hen the set up-bit is set at ?1?, the fo llow i ng conversion is performed on input signal. on 286 mv sync sy stem signals (nt s c composit e, yc signal, betacam signal ) w i th set up, luminance signal ( y ) : y = ( y- 42 ) / 0.925 ; chroma signal ( u / v ) : pb = pb / 0.925 ; pr = pr / 0.925 ; on 300 mv sync sy stems ( mii signal ) w i th set up , luminance signal ( y ) : y = ( y-41 ) / 0.925 ; chroma signal ( u / v ) : pb = pb / 0.925 ; pr = pr / 0.925 ; rev.0 62 2003/01
asahi kasei [AK8850] 7-4-19 t i ming out p ut t he AK8850 outputs the signals listed below . output logical states can be al tered by the [ out p ut cont rol regist e r ]. t he state show n is the default val ue (refer to the output t i ming diagram ). either the vsync or vd signals can be output on the vsync output pin per the register setting. out put timing of the field signal and the f r ame signal can be delay ed by 0.5 h time using the f f d elay-bit of the [ out p ut cont rol regist e r ]. csync signals can be output via the f r ame1 pin by setting the f rcsync-bit of the [ cont rol 1 regist e r ] bit-7. ffdelay-bit f unction 0 field/frame timing signal changes at t he falling edge of hsync of proper line. 1 f i eld/f r ame timing signal chages at the ra ising edge of serration pulse of proper line. frcsync-bit f unction 0 f r ame timing signal is output from f r ame1pin 1 csync timing signal is output from f r ame1pin at 525-line-sy stem input ( out put state at default value ) hsync : ? low ? level signal of 4.7 mi crosec. duration in 15.734 khz interval vsync : ? low ? output signal during line 4 ~ line 6 / line 266.5 ~ line 269.5 ( line 266.5 means from the latter 0.5 h time of line 266,and line 269.5 means up to the former 0.5 h time of line 269 ). vd : ? low ? output signal during line1 ~ line 9 / line263.5 ~ line 272.5 ( line 263.5 means from the latter 0.5 h time of line 263, and line 272.5 means up to the former 0.5 h time of line 272 ). f i eld : output signal to become ? low ? at odd f i elds, and ? high ? at even f i elds. frame : color frame f o r non-standard signal inputs, f i eld si gnal toggles at the rate of ( line numbers per each f r ame / 2 ). f r ame signal changes at the rate of line numbers per each f r ame ( f r ame signal c hanges state at line 4 ). csync : composite sy nc signal.c sync output does not change state. at 625-line-sy stem input ( output state at default value ) hsync : ? low ? level signal of 4.7 mi crosec. duration in 15.734 khz interval vsync : ? low ? output signal during line 1 ~ line 3.5 / line 313.5 ~ line 315 ( line 3.5 means up to the former 0.5 h time of line 3,and line 313.5 means from the latter 0.5 time of line 313 ). vd : ? low ? output signal during li ne 623.5 ~ line 5 / line 311 ~ line 318.5. ( line 632.5 means from the the latter 0. 5 h time of line 623, and line 318.5 means up to the former 0.5 h time of line 318 ). f i eld : output signal to become ? low ? on odd f i elds, and ? high ? on even f i elds. frame : color frame f o r non-standard signal inputs, f i eld si gnal toggles at the rate of ( line numbers per each f r ame / 2 ). f r ame signal changes state at the rate of line numbers per each f r ame ( f r ame si gnal changes state at line 1 ). csync : composite sy nc signal. csync output does not change state data at both rising edge and falling edge of the field signal is cb data. t he field si gnal and data relationship of standard signal inputs is as follow s . field cb cr y y cb d[7:0] c b0 y 0 c r 0 y 1 122t rev.0 63 2003/01
asahi kasei [AK8850] * [ out p ut cont rol regist e r ] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v d v s y n c f f d e l a y h a l f c l k f r a m e d v a l v l k f e i l d v s y n c h s y n c default value 0 0 0 1 0 1 0 0 logical state can be altered by these registers. default value is ? 0 ? as show n in the timing diagram. * [ cont rol 1 regist e r ] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r c s y n c d e c i m a t int p o l 1 int p o l 0 a g c c 1 a g c c 0 agct 1 agct 0 default value 1 0 0 0 0 0 0 0 f rcsync-bit controls output on f r ame 1 pin. 7-4-20 vlock funct ion t he AK8850 sy nchronizes its internal operati on w i th the input signal?s f r ame confi guration. f o r exampl e, if the input signal f r ame configuration consis ts of 525 lines, the internal operation uses t he 525 line configuration. t h is is called the vlock configuration. when the input signal configured w i th 525 line per frame is sw itched to 524 lines , the operation tracks to the sw itched input signal sy stem. in this case vlock function is put into un-locked state dur ing the tracking time. t he un-locked state is verified by the [ st at us 1 regist e r ]. vlock status is observed on the dvalid pin by setting the dval / vlk-bit of the [ out p ut cont rol regist e r ] ( r / w ) [ sub address 0x 05 ]. vlock status status 1 register vlock-bit vlock output pin locked (sy n chronaize w i th input video signal) 1 high unlocked un-sy n chronaized w i th input video signal 0 l o w t he transition timing of the vlock output pin changes w i th vlock configuration conditions. . rev.0 64 2003/01
asahi kasei [AK8850] 7-4-21 out p ut int e rf ace t he AK8850 outputs decoded data in it u-r bt .656 compatible interface formats, i.e., t he sample number for each line is guaranteed to be 858 / 864 ( 525 sy stem / 625 sy stem ) respectively . poor input quality or non line-locked/fram e-locked pll clocks may prevent it u-r bt .656 compatible output. , in these cases, the input signal and ou tput data are correlated by the follow i ng 2 methods, selected by the [ out p ut f o rmat regist e r ]. ( 1 ) adjust using a line-drop / repeat scheme ( number of lines is not equal to 525 / 625, but number of samples is guaranteed to be 858 / 864 ). t h is process is performed w hen the final stage output buffer of the devic e either overflow s or underflow s. ( 2 ) make 858 / 864 samples to be variable ( number of sa mples is not equal to 858 / 864, but number of lines is guaranteed to be 525 / 625 ). decoded data becomes it u-r bt . 656 compatible except for the last line of each f r ame ( line 3 in 525 sy stem , line 625 in 625 sy stem ).i.e., ty pical 858 / 864 samples per each li ne is guaranteed other than at li ne 3 / line 625 ( 525 sy stem / 625 sy stem ). t he number of samples at line 3 and line 625 is un-determi ned since it is decided by relationdhip betw een the input signal rate and the pll-generated clock rate (it hovers around 858 / 864 samples ). in this processing mode, there is less of a chance for buffer overflow or underflow since the buffer point er is moved to the mid point of the buffer at the last line. w hen either overflow or underflow occurs at the final stage buffer, a line drop / repeat function is processed ( w h ich can occur w hen the input signal rate differs mu ch from the pll-generated clock rate ). t he dvalid pin output is ? low ? during t he active-video period of the output data. relationship betw een hsync, dvalid and output data are show n below . clk27mout dvalid c b0 c r 0 y 0 y 1 c b1 y 2 c r 1 y 3 y 719 c r 359 y 718 d[7:0] video signal hsy n c active video start position normally , 123th/133th(525 sy stem/625 sy stem)pixel from 0h pixel f i ne-tuning the active-video start posit ion and a y / c delay amount to be out put can be accomplished by programming the [ out p ut format regist e r ]. rev.0 65 2003/01
asahi kasei [AK8850] output interface set register : output interface is set by the [ out p ut format regist e r ]. * [ out p ut format regist e r ] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 actsta[ 2 ] a c t s t a [ 1 ] a c t s t a [ 0 ] y cdelay [ 2] y cdelay [ 1] y cdelay [ 0] 601li mi t e r r h n d default value 0 0 0 0 0 0 0 0 [ errhnd ]-bit of the [ out p ut format regist e r ] controls error handling as follow s . * errhnd-bit errhnd-bit 0 number of sample is constant 525 sy stem : 858 samples 625 sy stem : 864 samples 1 number of line in a frame is constant 525 sy stem : 525line 625 sy stem : 625line f i ne-tuning of the start positi on is accomplished by programming the act s t a [2 :0 ]-bit. 122th sample (525 sy stem) 132th sample (625 sy stem) 0h point * act s t a [ 2 : 0 ]-bit set actsta2:actsta0 function note 100 525sy s tem : active video starts at the 119th sample 625sy s tem : active video starts at the 129th sample 101 525sy s tem : active video starts at the 120th sample 625sy s tem : active video starts at the 130th sample 110 525sy s tem : active video starts at the 121th sample 625sy s tem : active video starts at the 131th sample 111 525sy s tem : active video starts at the 122th sample 625sy s tem : active video starts at the 132th sample 000 525sy s tem : active video starts at the 123th sample 625sy s tem : active video starts at the 133th sample default 001 525sy s tem : active video starts at the 124th sample 625sy s tem : active video starts at the 134th sample 010 525sy s tem : active video starts at the 125th sample 625sy s tem : active video starts at the 135th sample 011 525sy s tem : active video starts at the 126th sample 625sy s tem : active video starts at the 136th sample a fine-tuning of the yc output timing is possible by se tting yc delay [ 2 : 0 ]-bit of the [ out p ut format regist e r ].t he yc delay fine-tuning bit is set in 2?s complement values. a c ts ta 2 : a c ts ta 0 f unction note 100 y data is delay ed 4samples (296nsec) agaist c-data 101 y data is delay ed 3samples (222nsec) agaist c-data 110 y data is delay ed 2samples (148nsec) agaist c-data 111 y data is delay ed 1sampl e (74nsec) agaist c-data 0 0 0 n o delay d e f a u l t 001 c data is delay ed 1sampl e (74nsec) agaist y-data 010 c data is delay ed 2samples (148nsec) agaist y-data 011 c data is delay ed 3samples (222nsec) agaist y-data rev.0 66 2003/01
asahi kasei [AK8850] 7-4-22 power save mode t he AK8850 is placed in pow e r save mode by setting the ps-bit of the [ power save mode regist e r ] to ? 1 ?. exiting pow e r save mode is done by setting the ps-bit to ?0?. during pow e r save mode, the i2c bus controller, clock output driver and vref generating circuit are active, the pll block is initializ ed and pll dac local code becomes 0x80. after exiting pow e r save mode, the device re-starts oper ation from the state w h ic h is set via the i2c bus. all circuits are put into sleep mode w hen the pow e r dow n pin ( pd ) is set to high. t he ivcxo output current is zero micro amps in this state. t o re-start the AK8850, an i nput reset and initialization are required after setting pd pin from high to low . operation is stabilized in a few milliseconds. please follow the pow e r dow n set sequence for proper setting. pow e r save mode related register : pow e r save related registers are progra mmed by the [ power save mode regist e r ]. * [ power save mode regist e r ] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r e s e r v e d r e s e r v e d r e s e r v e d pllrst a d c 3 a d c 2 a d c 1 p s default value 0 0 0 0 0 0 0 0 * ps-bit set ps-bit f unction note 0 n o r m a l f u n c t i o n 1 stops the clock supply to the inte rnal digital block, exclusive control block.. stops adc1/2/3. resets the pll control circuit. * adc1 / 2 / 3-bit set adc1/2/3-bit f unction note 0 adc1/2/3 active mode 1 adc1/2/3 sleep mode each adc can be set to sleep mode individually . rev.0 67 2003/01
asahi kasei [AK8850] 7-4-23 device cont rol int e rface t he AK8850 is controlled via the i2c bus interface. i2c control sequence slave address is selected to be eit her 0x88 or 0x8a by sela pin set. sela pull dow n(l) pull up(h) slave address 0 x 8 8 0 x 8 a sequential read: by host by AK8850 s,(rs) : start condition a : acknow ledge (sda low ) a : not acknow ledge (sda high) stp : stop condition r/w 1 : read 0 : w r ite s slave address w a sub address data_1 a a data_n a/a stp w r ite sequence: data2 a data ??????
asahi kasei [AK8850] 8. regist e r definit ion t he AK8850 has the follow i ng registers. sub address register default r/w f unction 0x00 input video standard register 0x00 r/w set input video standard 0x01 input signal select register 0x11 r/w select input video signal 0x02 vertical blanking length regist er 0x14 r/w set vbi interval 0x05 output control register 0x14 r/ w set the attribution of output data 0x06 output f o rmat register 0x00 r/w set the output i/f 0 x 0 8 c o n t r o l - 1 r e g i s t e r 0 x 8 0 r / w control r e g i s t e r 0 x 0 9 c o n t r o l - 2 r e g i s t e r 0x c 1 r / w control r e g i s t e r 0x0a clamp control register 0x00 r/w set the clamp function setting 0 x 0 b c l a m p t i ming control register 0x11 r/w set the clamp pulse timing 0x0c clamp t i ming 2 control register 0x1c set the clamp pulse timing 0x0d pga1 gain control register 0x 40 r/w set the manual gain of pga1 0x0e pga2 gain control register 0x 40 r/w set the manual gain of pga2 0x0f pga3 gain control register 0x 40 r/w set the manual gain of pga3 0x10 y/c separation control r e g i s t e r 0 x 0 6 r/w set t he yc separation function 0x11 color killer control register 0xad r/w color killer setting 0x12 brightness control register 0x00 r/w set brightness adjustment 0x13 contrast control register 0x80 r/w set contrast adjustment 0x14 saturation control register 0x80 r/w set saturation adjustment 0x15 hue control register 0x00 r/w set hue adjustment 0x1c pow e r save register 0x00 r/w pow e r save setting 0x1f request vbi info regist er 0x00 w vbiddata decode requet 0x20 status 1 register 0x00 r internal status of AK8850 0x21 status 2 register 0x00 r nternal status of AK8850 0x22 closed caption1 register 0x00 r closed caption data 0x23 closed caption2 register 0x00 r closed caption data 0x24 extended data 1 register 0x 00 r closed caption extended data 0x25 extended data 2 register 0x 00 r closed caption extended data 0x26 vbid1 register 0x00 r vbid data 0x27 vbid2 register 0x00 r vbid data 0x28 w ss1 register 0x00 r w ss data 0x29 w ss2 & aspect data register 0x00 r w ss data and video aspect data. 0x2e device/revision id register 0x 00 r device id / revision id 0x36 clock control-1 register 0x84 r/w clock transition control register. 0x37 clock control-2 register 0x7c r/w clock transition control register. 0x38 clock control-3 register 0x3c r/w clock transition control register. clock control-4 register 0xdc r/ w 0x3a clock control-5 register 0x04 r/w clock transition control register. 0x46 pll control register 0x 00 r/w pll control register 0x47 pll dac set register 0x80 r/w pll_dac setting register 0x39 clock transition control register. rev.0 69 2003/01
asahi kasei [AK8850] input video sta nda rd register ( r / w )[ sub a ddress 0x00 ] t h is register sets the input video signal standard. automatic setup recognition is not available. reserved bits must be set to ? 0 ?. su b a d d r ess 0x00 defau l t valu e : 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r e s e r v e d nent b / w set u p v s 3 v s 2 v s 1 v s 0 default value 0 0 0 0 0 0 0 0 input video standard register definition bit register name definition bit 0 ~ bit 3 video standard bit r/w vs3 vs0 AK8850 can deal w i th only component signal for 625- video ssy tems. vs0 ~ vs3 set the input video standard 0000 : nt sc/ 525component 1111 : 625component other settings are reserved. bit 4 set up setup bit r/w 0 : w i thout setup [default] 1 : w i th setup bit 5 0 : color video signal is input [default] b/w black & w h ite bit r/w b/w video signal setting 1 : b/w video signal is input bit 6 nent component video sel bit r/w set the component video signal 0 : mii level component video signal [default] 1 : bet acam level component video signal bit 7 reserved reserved bit r/w reserved bit r/w setting component input is done as follow s . 1. component input is selected via the input signal select register. 2. selection of mii or betacam is done by the input video standard register nent -bit. 3. set either 525- or 625 line sy stems. rev.0 70 2003/01
asahi kasei [AK8850] input signa l select register ( r / w ) [ sub a ddress 0x01 ] register to select the input signal. su b a d d r ess 0x01 defau l t valu e : 0x11 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r e s e r v e d r e s e r v e d s y n c i n 1 s y n c i n 0 i n s e l 3 i n s e l 2 i n s e l 1 i n s e l 0 default value 0 0 0 1 0 0 0 1 input select register definition bit r/w definition bit 0 ~ insel0 0111 : ain3 y ain6 v bit 3 ~ insel3 input select bit r/w select the input video signal insel3 insel0 0000 : no input 0001 : ain1 composite [default] 0010 : ain2 composite 0011 : ain3 composite 0110 : ain2 y ain4 c a i n 5 c 1011 : ain3 y ain5 u bit 4 ~ syncin1 r/w bit 5 syncin0 syncin select bit select the video signal for the clamp timing generator. sync1: sync0 00 : no input 01 : sync1 timing [default] 10 : sync2 timing 11 : sync3 tiimng bit 6 bit 7 reserved reserved bit r/w reserved bit register name supplement bit3 - bit0 bit3= 1 : component , bit2= 1 : y/c v i deo input rev.0 71 2003/01
asahi kasei [AK8850] vertica l bla nking length register ( r / w ) [ sub a ddress 0x02 ] register to set vbi interval. su b a d d r ess 0x02 defau l t valu e : 0x14 bit 7 bit 6 bit 5 bit 3 bit 2 bit 1 v b i d e c t r s v s e l h a l f s u v b i l 4 v b i l 3 v b i l 2 v b i l 1 v b i l 0 default value 0 0 0 1 0 1 0 0 bit 4 bit 0 vertical blanking register definition bit register name r/w definition bit 0 - bit 4 vbil4 vbil0 vertical blanking information length bit r/w set the vbi interval default value is 20 (decimal) t he value of vbi[4:0] must be set more than 10. i.e., active video starts from line-21 bit 5 half su half setup bit r/w set the setup function for the first active line of the 2nd field. 0 : 0.5h of 2nd field is not made setup process. 1 : 0.5h of 2nd field is made setup process. t r svsel t i me reference signal v select bit r/w set the v-bit transition timing for eav/sav. nt sc, 525 component t r svsel = 0 : line 1-9 / line264-line272 : v= 1 other v= 0 t r svsel = 1: line 1-19 / line 264-line282 v= 1 other v= 0 625 sy tem : v-bit setting should reflect t r svsel-bit setting bit 7 vbidec vbi decode bit r/w output data w h ile the vbi interval. c = 0x80 0 : y = 0x10 1 : y = input data(same as b/w process) c = 0x80 bit 6 f o r details, please refer to section 7-4-10 vert i cal blanking int e rval. rev.0 72 2003/01
asahi kasei [AK8850] output control register ( r / w ) [ sub a ddress 0x05 ] t h ie register sets the ex ternal output signal attributes like hsync, vsync, fi eld, dvalid and frame etc. t i ming of output signals can be altered by clkout -bit set. su b a d d r ess 0x05 defau l t valu e : 0x14 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v d v s y n c f f d e l a y h a l f c l k f r a m e d v a l v l k f i e l d v s y n c h s y n c default value 0 0 0 1 0 1 0 0 output control register definition bit register name definition bit 0 0 : low [default] hsync hsync-logic bit r/w 1 : high bit 1 r/w 1 : high vsync vsync-logic bit 0 : low [default] bit 2 r/w fiel d f i eld-logic bit 0 : odd field : low 1 : odd f i eld : high [default] bit 3 dval/vlk dvalid vlock sw itch- bit r/w 0 : dvalid signal output [default] 1 : vlock status output bit 4 frame f r ame-logic bit r/w 0 : low at cf = 0 1 : high at cf = 0[default] bit 5 halfclk halfclk-bit r/w 0 : low at y-data ouput timing [ default] 1 : hight at y-data output bit 6 ffdelay f i eld f r ame delay bit r/w f i eld timing signal and f r ame timing signal can be output 0.5h delay ed w i th this bit. 0 : no delay [default] bit 7 vdvsync vd/vsync select bit r/w 0 : output vsync pulse [default] 1 : ouput vd pulse. (refer to the f i gure ?output timing signal?) r/w 1 : 0.5h delay f i eld and f r ame signals are correct values only w hen the st andard signal is input. ( in case of non-standard signal input, f i eld and f r ame signals are not necessarily correct ones .f or handling of non-standard signal input,refer to item 7-4-21 ). rev.0 73 2003/01
asahi kasei [AK8850] output forma t register ( w / r ) [ sub a ddress 0x06 ] register to set output format. su b a d d r ess 0x06 defau l t valu e : 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 1 act s t a 2 a c t s t a 1 act s t a 0 y c d e l a y 2 errhnd y c d e l a y 1 y c d e l a y 0 601limit default value 0 0 0 0 0 0 bit 2 bit 0 0 0 output f o rmat register definition bit register name r/w definition bit 0 errhnd error handling bit r/w setting the data handling procedure w hen AK8850 cannot output the dat a follow to it u-r. bt.656. error handling normally occurs w i thin the last lines of the f r ame. 0 : line drop/repeat 1 : number of smaples of the line is change. bit 1 601limit 601 output limit bit r/w min/max value of the output data 0 : 1~ 254 (y/cb/cr) [default ] 1 : 16~ 235 (y) 16~ 240 (cb/cr) bit 2 ~ bit 4 ycdelay0 - ycdelay2 one delay time is 74nsec(1clock@13.5mhz) [ycdelay2-ycdelay0]= 111 : y-data is 1clock delay against c-data y/c delay control bit r/w y/c delay setting for output data. set the value w i th 2?s complement 101 : y-data is 3clocks delay against c-data 110 : y-data is 2clocks delay against c-data 000 : no delay [default] 001 : c-data is 1clock delay against y-data 010 : c-data is 2clocks delay against y-data 011 : c-data is 3clocks delay against y-data bit 7 a c ts ta 0 active video start control bit set fine adjustment of start position of decoded video data. set the value w i th 2?s complement 011 : decoding the video data 3pixels delay ed. bit 5 ~ - a c ts ta 2 r/w [act st a2:act st a0]= 101 : decoding the video data 3pixels earlier. 110 : decoding the video data 2pixels earlier. 111 : decoding the video data 1pixel earlier. 000 : normal position [default] 001 : decoding the video data 1pixel delay ed. 010 : decoding the video data 2pixels delay ed. rev.0 74 2003/01
asahi kasei [AK8850] control 1 register / control 2 register t hese registers contro l the AK8850 operations. t here are 2 registers, cont ro l 1 and cont rol 2. reserved bits must be set to ? 0 ?. co n t ro l 1 reg i ster (r/w ) [su b a d d r ess 0x08] su b a d d r ess 0x08 default value : 0x80 bit 7 bit 6 bit 5 bit 3 bit 2 bit 1 bit 0 f r c s y n c r e s e r v e d int p o l 1 int p ol0 agcc1 agcc0 agct 1 agct 0 default value 1 0 0 bit 4 0 0 0 0 0 control 1 register definition bit register name r/w definition bit 0 ~ agct 0 agc t i me constant control bits 11 : slow [t = 29f ield] bit 1 ~ agct 1 r/w set the agc time constant. w hen the agc is disabl ed, each pga can be set manually . [agct 1 agct 0] = 00 : disable [default] 01 : fast [t = 1field] 10 : middle [t = 7f ield] (t : t i me constance) bit 2 ~ bit 3 agcc0 ~ agcc1 agc coring control bits r/w set the non-sensing bandw idth of agc [agcc1 agcc0] = 00 : no non-sensing bandw idth[default] 01 : 1bit 10 : 2bits 11 : 3bits bit 4 ~ bit 5 int p ol0 int p ol1 interpolator control bit r/w setting for pixel interpolator [int p ol1 int p ol0] = 00 : auto [default ] 01 : on 10 : of f 11 : reserved setting to automode, the interpolator sw itch turns on/off according to the clock mode as described bellow , line lock pll : of f f r ame lock pll: on f i xed clock mode: on bit 6 reserved reserved r/w reserved bit 7 frcsync frame csync sw itch bit r/ w define the output dat a from f r ame1pin. 0 : f r ame timing pulse output 1 : csync timing pulse output [default] rev.0 75 2003/01
asahi kasei [AK8850] co n t ro l 2 reg i ster (r/w ) [su b a d d r ess 0x09] su b a d d r ess 0x09 defau l t valu e : 0xc1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 clkmo d e1 clkmode0 acc1 acc0 dpcc1 dpcc0 dpct 1 dpct 0 default value 1 1 0 0 0 0 0 1 control 2 register definition bit register name r/w bit 0 ~ bit 1 dcpt 0 ~ dpct 1 digital pedestal clamp t i ming bit r/w setting of t i me constant of the digital pedestal clamp. dpct 1:dpct 0 00 : digital pedestal clamp of f 01 : f a st [default] 10 : middle 11 : slow bit 2 ~ bit 3 dpcc0 ~ dpcc1 digital pedestal clamp coreing bit setting the non-sensing bandw idth of digital pedestal clamp. dpcc1 : dpcc0 00 : no non-sensing bandw idth [default] 01 : 1bit 10 : 2bits 11 : 3bits bit 4 ~ bit 5 acc0 ~ acc1 auto color control bits r/w setting the accf function [acc1 acc0] = 00 : disable acc [default] 01 : f a st [t = 2-f i eld] 10 : middle [t = 8-f i eld] 11 : slow [t = 30-f i eld] (t : t i me constance) bit 6 ~ bit 7 clkmode0 ~ clkmode1 clock mode bits r/w setting clock mode clkmode1: clkmode0 = 00 : f i xed clock mode(27mhz) 01 : line-locked clock mode 10 : f r ame-locked clock mode 11 : clock mode auto select mode [default] definition rev.0 76 2003/01
asahi kasei [AK8850] cla m p control register ( r / w ) [ sub a ddress 0x0a ] t h is register controls clamp-related matte rs. reserved bits must be set to ? 0 ?. su b a d d r ess 0x0a defau l t valu e : 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 a c l m p inclpt m g f b c l p t m g 1 f b c l p t m g 0 c l p l v l 1 c l p l v l 0 default value 0 0 0 0 0 0 0 0 unmask reserved clamp control register bit register name r/w definition bit 0 bit 1 clplvl0 ~ clplvl1 clamp level 0 ~ clamp level1 bit r/w setting analog video clamp. t h is setting is valid for clamp 1. t he level of clamp 2/3 is constant at 512 level. clplvl1 clplvl0 00: 16 [default] 01: 240 10: 252 11: analog clamp is off bit 2 bit 3 fbcl pt mg0 ~ fbcl pt mg1 f eed back clamp t i ming bit r/w setting the clamp timing pulse. 00 : sy nctip level clamp w i th the internal clamp timing [default] 01 : sy nctip level clamp w i th the external clamp timing pulse. 10 : pedestal level clamp w i th the internal clamp timing pulse. 11 : pedestal level clamp w i th the external clamp timing pulse. bit 4 inclpt mg input clamp t i ming bit setting the clamp timing pulse. 0 : internal clamp timing pulse [default] 1 : external clamp timing pulse bit 5 aclamp analog clamp on/off bit r/w setting the clamp on/off. w hen a video signal is input through ac coupling capacitor, this set must be set to ?0?. 0 : on [default] 1 : off (ain clamp off) bit 6 reserved reserved bit r/w reserved bit 7 unmask clamp unmask bit r/w clamp mask on/off bit. normally this bit set to 0. 0 : masked [default] 1 : unmasked rev.0 77 2003/01
asahi kasei [AK8850] cla m p timing 1 control register ( r / w ) [ sub a ddress 0x0b ] t h is register sets sync-t i p clamp timing. clamp t i ming pulse generation and its pul se w i dth can be adjusted. output signal mode selection of the ext c lp pin is also possible. f o r a timing diagram, refer to the sync separation description in the clamp section. re served bits must be set to ? 0 ?. su b a d d r ess 0x0b defau l t valu e : 0x11 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ext c l p 1 e x t c l p 0 sclpw i d t h 2 s c l p w i d t h 1 s c l p w i d t h 0 sclpstat2 sclpstat1 sclpstat0 default value 0 0 0 1 0 0 0 1 clamp t i ming control register bit register name r/w definition setting the start position of sy nctip clamp pulse bit 0 sclpst at 0 sclpst at 2 default value is sclpst a2 : sclpst a0 = 001 [sclpst at 2 sclpst at 0 ] 000 : 2clks later 001 : 4clks later 011 : 8clks later 100 : 10clks later 101 : 12clks later 111 : 16clks later 1clk is about 37[nsec] r/w sy nctip clamp start timing0 sy nctip clamp start timing2 bit bit 2 010 : 6clks later 110 : 14clks later sclpwidt h0 sy nctip clamp pulse w i dth0 bit sy nctip clamp pulse w i dth2 bit r/w sclpw i dt h2 : sclpw i dt h0 = 010. [sclpwidt h 3 sclpwidt h0] 001 : 4 clks (148nsec) 010 : 8 clks (296nsec) 011 : 16 clks (592nsec) 100 : 24 clks (888nsec) 101 : 32 clks (1.18usec) 110 : 40 clks (1.48usec) 111 :48 clks (1.78usec) setting the sy nctip clamp pulse w i dth default value is bit 3 sclpwidt h2 bit 5 000 : 2 clks (74nsec) bit 6 setting the output the timing data from ex t c lp-pin. 00 : hi-z (defaul) 11 : syncdet signal r/w external clamp 0 bit ext c lp0 external clamp 1 bit ext c lp1 bit 7 [ex t clp1:ex t clp0] 01 : internal sy nctip clamp timing pulse. 10 : internal pedestal clamp timing pulse. rev.0 78 2003/01
asahi kasei [AK8850] cla m p timing 2 control register ( r / w ) [ sub a ddress 0x0c ] t h is register sets the pedestal clamp timing. t he timing of the clamp t i ming pulse generat ion and its pulse w i dth can be adjusted. su b a d d r ess 0x0c defau l t valu e :0x1c f o r timing diagram,refer to the sync-separ ation description in the clamp section. reserved bits must be set to ? 0 ?. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 s l c l v 1 s l c l v 0 p c l p w i dth0 p c l p s t a t 2 p c l p s t a t 1 p c l p s t a t 0 pclpw i d t h 2 p c l p w i d t h 1 default value 0 0 0 0 0 1 1 1 clamp t i ming 2 control register register name r/w definition bit 0 pclpst at 0 pclpst at 2 pedestal clamp start timing0 bit pedestal clamp start timing2 bit r/w setting the start position of pedestal clamp pulse. default value is pclpst a2 : pclpst a0 = 100 [pclpst at 2 pclpst at 0] 001 : 126 clks (4.65usec) later 010 : 132 clks (4.88usec) later 011 : 140 clks (5.18usec) later 100 : 148 clks (5.48usec) later 101 : 156 clks (5.77usec) later 110 : 164 clks (6.07usec) later 111 : 172 clks (6.36usec) later bit 3 bit 5 pclpwidt h0 pclpwidt h3 pedestal clamp pulse w i dth0 setting the pedestal clamp timing pulse w i dth. default value is pclpw i dt h2 : pclpw i dt h0 = 011 [pclpwidt h 3 pclpwidt h0] 000 : 16 clks (592 nsec) bit 000 : 118 clks (4.37usec) later bit 2 1clk is about 37[nsec] pedestal clamp pulse w i dth3 bit 100 : 40 clks (1.48 usec) 111 : 52 clks (1.92 usec) 001 : 24 clks (888 nsec) r/w 010 : 28 clks (1.04 usec) 011 : 32 clks (1.18 usec) 101 : 44 clks (1.63 usec) 110 : 48 clks (1.78 usec) setting the slice level default value is 00 [slclv1:slclv0] = slclv0 bit 6 00 :sliced 1/4 level above the sy nctip slice level control bit r/w 01 :sliced 1/2 level above the sy nctip slclv1 bit 7 10 :prohibit to set 11: sliced 3/8 level above the sy nctip rev.0 79 2003/01
asahi kasei [AK8850] pga 1 gain co n t ro l reg i ster (r/w ) [su b a d d r ess 0x0d] su b a d d r ess 0x0d defau l t valu e : 0x40 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r e s e r v e d p g a 1 [ 6 ] pga1[5 ] p g a 1 [ 4 ] p g a 1 [ 3 ] p g a 1 [ 2 ] p g a 1 [ 1 ] p g a 1 [ 0 ] default value 0 1 0 0 0 0 0 0 pga1 gain control register bit register name r/w definition bit 0 bit 6 pga1[0] pga1[6] pga1[0] pga1[6] bit r/w setting pga1 gain. t h is register is available w hen control 1 register is set to [bit-1 ,0] = [0,0] (agc disable) gain step of pga is about 0.1db/lsb. bit 7 reserved reserved r/w reserved pga 2 gain co n t ro l reg i ster (r/w ) [su b a d d r ess 0x0e] su b a d d r ess 0x0e defau l t valu e : 0x40 bit 7 bit 6 bit 5 bit 4 bit 2 bit 1 bit 0 r e s e r v e d p g a 2 [ 6 ] pga2[5 ] p g a 2 [ 4 ] bit 3 p g a 2 [ 3 ] p g a 2 [2] pga2[1] pga2[0] default value 1 0 0 0 0 0 0 pga2 gain control register r/w definition bit 0 pga2[0] pga2[0] 0 bit register name setting pga2 gain. r/w t h is register is available w hen control 1 register is set to [bit-1 ,0] = [0,0] (agc disable) gain step of pga is about 0.1db/lsb. pga2[6] bit pga2[6] bit 6 bit 7 reserved reserved r/w reserved pga 3 gain co n t ro l reg i ster (r/w ) [su b a d d r ess 0x0f ] su b a d d r ess 0x0f defau l t valu e : 0x40 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r e s e r v e d p g a 3 [ 6 ] pga3[5 ] p g a 3 [ 4 ] p g a 3 [ 3 ] p g a 3 [ 2 ] p g a 3 [ 1 ] p g a 3 [ 0 ] default value 0 1 0 0 0 0 0 pga3 gain control register bit register name r/w definition 0 bit 0 bit 6 pga3[0] pga3[6] pga3[6] bit r/w setting pga3 gain. t h is register is available w hen control 1 register is set to [bit-1 ,0] = [0,0] (agc disable) gain step of pga is about 0.1db/lsb. pga3[0] bit 7 reserved reserved r/w reserved rev.0 80 2003/01
asahi kasei [AK8850] yc sepa ra tion control 1 register ( r / w ) [ sub a ddress :0x10 ] t h is register sets yc separation- related matters. su b a d d r ess 0x10 defau l t valu e : 0x06 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 r e s e r v e d r e s e r v e d r e s e r v e d r e s e r v e d c b p f s 1 c b p f s 0 y c s e p 1 bit 0 y c s e p 0 default 0 0 0 0 0 1 0 yc separation control register definition bit register name r/w 1 definition 11 : reserved bit 0 ~ bit 1 yc separation bit ycsep0 ~ ycsep1 r/w setting yc separation ycsep1 ycsep0 00 : 2d yc-separation 01 : 1d yc-separation 10 : adaptive y/cseparation [default] bit 2 ~ bit 3 cbpfs0 ~ c band pass f ilter select bit cbpfs1 r/w setting the bandw idth of chrominance signal cbpfs1:cbpfs0 00 : reserved 01 : w i de [default] 10 : middle 11 : narrow rev.0 81 2003/01
asahi kasei [AK8850] color killer control register (r/w) [sub a ddress 0x1 1] su b a d d r ess 0x11 defau l t valu e : 0xa d bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 c l _ k i l l r e s e r v e d c k l v l 5 cklv l 4 c k l v l 3 c k l v l 2 c k l v l 1 c k l v l 0 1 0 1 0 1 1 0 1 default value color killer control register definition bit register name r/w definition bit 1 ~ bit 5 cklvl0 cklvl5 color killer level r/w setting the color killer level. t he range of color killer level is from -17db to - f w i th 63 step. 0 : - ? db 63 : -17db default value is 45 (-20db) setting value is defined as follow i ng formula color killer l e v e l i s c k l [ d b ] . setting value = 10 ck l / 2 0 * 448 bit 6 reserved reserved bit r/w reserved bit 7 cl-kill color killer bit r/w color killer sw itch 0 : color killer disable. 1 : color killer enable[default] rev.0 82 2003/01
asahi kasei [AK8850] brightness control register ( r / w ) [ sub a ddress 0x12 ] t h is register controls the brightness adjustment. default value ( 0x00 ) corresponds to un-adjusted condition. su b a d d r ess 0x12 defau l t valu e : 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b r 7 b r 6 b r 5 b r 4 b r 3 b r 2 b r 1 b r 0 default value 0 0 0 0 0 0 0 0 brightness control register definition bit r/w definition bit 0 ~ bit 7 br0 ~ br7 brightness control bit r/w brightness level is defined follow i ng formula -286mv sy nc signal (w ithout setup) 1 [br7:br0]*100/255 -286mv sy nc signal (w ith setup) 1 [br7:br0]*108/255 1 [br7:br0]*111/255 -300mv sy nc signal (w ithout setup) 1 [br7:br0]*102/255 -300mv sy nc signal (w ith setup) register name contra st control register ( r / w ) [ sub a ddress : 0x13 ] t h is register controls the contrast adjustment. default value ( 0x80 ) corresponds to un-adjusted condition. su b a d d r ess 0x13 defau l t valu e : 0x80 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cont 7 c o n t 6 cont 5 c o n t 4 cont 3 c o n t 2 cont 1 c o n t 0 default value 1 0 0 0 0 0 0 0 contrast control register definition bit register name r/w definition bit 0 ~ bit 7 cont 0 ~ cont 7 contrast control bit r/w contrast adjustment r ange is 0 to 2 by 1/256 step. rev.0 83 2003/01
asahi kasei [AK8850] sa tura tion control register ( r / w ) [ sub a ddress : 0x14 ] t h is register controls saturation adjustments. default value ( 0x80 ) corresponds to un-adjusted condition. su b a d d r ess 0x14 defau l t valu e : 0x80 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 0 s a t 6 sat 5 s a t 4 s a t 3 sat 2 s a t 1 s a t 0 default value 1 0 0 0 0 0 0 0 bit 1 sat 7 saturation control register definition bit register name r/w definition bit 0 ~ bit 7 sat 0 ~ sat 7 saturation control bit r/w saturation adjustment range is 0 to 2 by 1/256 step. it corresponds to the range betw een -
asahi kasei [AK8850] power sa ve register ( r / w ) [ sub a ddress : 0x1c ] controls the transition to pow e r save mode. recovery fr om the pow e r save mode is done by w r iting ? 0 ? to ps-bit. su b a d d r ess 0x1c defau l t valu e : 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r e s e r v e d r e s e r v e d r e s e r v e d pllrst a d c 3 a d c 2 a d c 1 p s default value 0 0 0 0 0 0 0 0 pow e r save register definition bit register name r/w definition bit 0 ps pow e r save bit r/w pow e r save mode setting register bit 0 : sw itch to the active mode from the pow e r save mode 1 : sw itch to the pow e r save mode bit 1 adc1 ad1 save bit r/w pow e r save mode for adc1 0 : sw itch to the active mode 1 : sw itch to the pow e r save mode bit 2 adc2 adc2 save bit r/w pow e r save mode for adc2 0 : sw itch to the active mode 1 : sw itch to the pow e r save mode bit 3 adc3 adc3 save bit pow e r save mode for adc3 0 : sw itch to the active mode 1 : sw itch to the pow e r save mode bit 4 pllrst pll reset bit r/w reset the pll control circuit. set to ?1 ? and set to ?0? after setting ?1?. bit 5 bit 7 r e s e r v e d r e s e r v e d bit r/w r e s e r v e d rev.0 85 2003/01
asahi kasei [AK8850] request vbi info register ( w ) [ sub a ddress : 0x1f ] t h is register controls vbi operations, includi ng closed- caption, ex tended data, vbid and w ss. t he AK8850 is put into a w a it condition for eac h data w hen ? 1 ? is w r itten into each bit. w hen the decoding is completed, ? 1? is w r itten into eac h bit of the [ st at us 2 regist e r ] and the decoded data are stored in the closed-caption data1 / data2,ccext ended data1 / data2,vbid data1 / dat a2 and w ss data1 / data2 registers respectively . su b a d d r ess 0x1f bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r e s e r v e d r e s e r v e d r e s e r v e d w s s r q v b i d r q ext r q c c r q aspectrq default value 0 0 0 0 0 0 0 0 request vbi info register definition bit register name r/w definition bit 0 aspect r q aspect request bit w request to decode aspect signal 0 : 1 : request bit 1 ccrq closed caption request bit w request to decode closed caption data 0 : 1 : request bit 2 w ex t r q extended data request bit request to decode extended data 0 : 1 : request bit 3 vbidrq vbid request bit w request to decode vbid data 0 : 1 : request bit 4 wssrq w ss request bit w request to decode w ss data 0 : 1 : request bit 5 bit 7 reserved reserved bit w reserved bit rev.0 86 2003/01
asahi kasei [AK8850] sta t us 1 register ( r ) [ sub a ddress 0x20 ] t h is register show s the inte rnal status of the AK8850. su b a d d r ess 0x20 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 c o l k i l f i e l d s c l k m o d e 1 s c l k m o d e 0 v s q l y f r m s t d v l o c k n o s i g status 1 register definition bit register name r/w definition bit 0 nosig no signal indicates bit r no signal indicates t h is data also output from nsig pin. 0 : signal is input 1 : no signal is input bit 1 vlock vsy n c lock indicates bit r show s sy nchronization st ates of the input signal. 0 : unsy nchronaized to the input signal. 1 : sy nchronaized to the input signal. bit 2 f r mst d f r ame standard indicates bit r show ing the input video signal quality . 0 : not 525/625 interlace video signal. 1 : 525/625 is interlace video signal. bit 3 nst d non standard signal indicates bit r show ing the input video signal quality . t h is bit reflects the sch status. f o r component video signal input, this bit depends on f r mst d -bit. (t his bit becomes 0 at frmst d -bit is 1) t he data of this bit is also output from nst d pin 0 : standard signal is input. 1 : non-standard signal is input. bit 4 bit 5 sclkmode0 sclkmode1 status current clock mode bit r show ing the clock-mode. [ clkmode1:clkmode0 ] = 00 : w o rking w i th f i xed clock mode. 01 : w o rking w i th line-locked clock mode 10 : reserved 11 : w o rking w i th f r ame-locked clock mode bit 6 f i eld f i eld status bit show ing the f i eld status 0 : odd f i eld 1 : even field bit 7 colkil color killer active bit r show ing the color killer status 0 : color killer is not active 1 : color killer is active rev.0 87 2003/01
asahi kasei [AK8850] sta t us 2 register ( r ) [ sub a ddress 0x21 ] t h is register indicates the inter nal status of the AK8850. su b a d d r ess 0x21 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 a p s 1 a p s 0 r e s e r v e d w s s vbid ex t c c aspect status 2 register definition bit register name r/w definition bit 0 aspect aspect detect bit r status of apsect signal. 0 : low (normal ) 1 : high (w ide) bit 1 cc closed caption detect bit r closed caption data detect bit 0 : closed caption is not detected. 1 : closed caption is found. bit 2 ex t extended renew al bit r extended data detect bit 0 : extended data is not detected. 1 : extended data is found. bit 3 vbid vbid renew al bit r vbid data detect bit 0 : vbid data is not detected. 1 : vbid data is found. bit 4 wss w ss renew al bit r wss data detect bit. 0 : w ss data is not detected. 1 : w ss data is found. bit 5 bit 7 r e s e r v e d r e s e r v e d b i t r r e s e r v e d rev.0 88 2003/01
asahi kasei [AK8850] closed-ca p tion 1 register / closed-ca p tion 2 register ( r ) [ sub a ddress 0x22 / 0x23 ] t hese registers show the closed-capt ion information w h ich is encoded on line 21 / 22 ( 525 sy stem / 625 sy stem ). su b a d d r ess 0x22 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 c c 7 c c 6 c c 5 c c 4 c c 3 c c 2 c c 1 c c 0 su b a d d r ess 0x23 bit 7 bit 6 bit 4 bit 3 bit 2 bit 1 c c 1 5 c c 1 4 cc13 cc12 cc11 c c 1 0 c c 9 c c 8 bit 5 bit 0 closed caption 1 register definition bit register name r/w definition bit 0 ~ bit 7 cc0 ~ cc7 closed caption data bit r closed caption data closed caption 2 register definition bit r e g i s t e r n a m e r/w d e f i n i t i o n ~ bit 7 cc8 ~ cc15 closed caption data bit r closed caption data bit 0 extended da ta 1 register / extended da ta 2 register ( r ) [ sub a ddress 0x24 /0x25 ] t hese registers show the ext e nded dat a information w h ich is encoded on line 284 / 335 ( 525 sy stem / 625 sy stem ). su b a d d r ess 0x24 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ex t 7 ex t 6 e x t 5 ex t 4 e x t 3 e x t 2 ex t 1 e x t 0 su b a d d r ess 0x25 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ext 1 5 e x t 1 4 ext 1 3 e x t 1 2 ex t 1 1 e x t 1 0 ex t 9 ex t 8 extended dat a 1 register definition bit register name r/w definition bit 0 ~ bit 7 ex t 0 ~ ex t 7 extended data bit r extended data extended dat a 2 register definition bit register name r/w definition bit 0 ~ bit 7 ex t 8 ~ ext 15 extended data bit r extended data rev.0 89 2003/01
asahi kasei [AK8850] vbid 1 register / vbid 2 register ( r ) [sub a ddress 0x26 / 0x27 ]. t hese registers show the vbid information w h ich is encoded on line 20 / 20 and line 283 / 333 ( 525 sy stem / 625 sy stem ). su b a d d r ess 0x26 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v b i d 7 v b i d 8 v b i d 9 v b i d 1 0 v b i d 1 1 v b i d 1 2 v b i d 1 3 v b i d 1 4 su b a d d r ess 0x27 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r e s e r v e d r e s e r v e d v b i d 1 vbid2 v b i d 3 v b i d 4 v b i d 5 v b i d 6 vbid 1 register definition bit register name r/w definition bit 0 ~ bit 7 vbid14 ~ vbid7 vbid data bit r vbid data vbid 2 register definition bit register name r/w definition bit 0 ~ bit 5 vbid6 ~ vbid1 vbid data bit r vbid data bit 6 bit 7 reserved reserved bit r reserved bit wss 1 register / wss 2 & a spect da ta register ( r )[ sub a ddress 0x28 / 0x29 ] t hese registers show w ss information encoded on line 23. su b a d d r ess 0x28 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 g 2 - 7 g 2 - 6 g 2 - 5 g 2 - 4 g 1 - 3 g 1 - 2 g 1 - 1 g 1 - 0 su b a d d r ess 0x29 bit 7 bit 6 bit 5 bit 3 bit 2 bit 1 aspdat r e s e r v e d g 4 - 1 3 g 4 - 1 2 g 4 - 1 1 g 3 - 1 0 g 3 - 9 g 3 - 8 bit 4 bit 0 w ss 1 register definition bit register name r/w definition bit 0 ~ bit 3 g1-0 ~ g1-3 group1 data bit r w ss group 1 data (aspect ration) bit 4 bit7 g2-4 g2-7 group2 data bit r w ss group 2 data (enhanced services) w ss 2 & aspect dat a register definition bit register name r/w definition bit 0 ~ bit 2 g3-8 ~ g3-10 group3 data bit r w ss group 3 data (subtitles) bit 3 bit 5 g4-11 g4-13 group4 data bit r w ss group 4data (reserved) bit 6 reserved reserved bit r reserved bit aspdat aspect data bit video aspect data bit 7 r rev.0 90 2003/01
asahi kasei [AK8850] device & revision id register ( r ) [ sub a ddress 0x2e ] t h is register indicates the device id and revision number of the AK8850. su b a d d r ess 0x2e t he device id is 0x00. t he initial revision number is 0x00. revision number is renew ed only w hen the control softw are needs to be modified. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 d i d 3 d i d 2 did1 did0 rev0 r e v 3 r e v 2 r e v 1 revision register definition bit register name r/w bit 0 ~ bit 3 rev0 ~ rev3 revision bit r indicates revision data rev3 rev0 0x00 bit 4 bit 7 did0 did3 device id r indicates device id AK8850 is 0x00 definition rev.0 91 2003/01
asahi kasei [AK8850] clock control-1 register ( r /w ) [ sub a ddress 0x36 ] t h is register controls the clock transition time in auto clock mode w h ich is set by [ bit 7 : bit 6 ] of the auto select ( cont rol 2 regist e r ( 0x09 )) su b a d d r ess 0x36 defau l t valu e : 0x84 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t t c 0 s k e w t h 4 s k e w t h 3 skewt h 2 s k e w t h 1 s k e w t h 0 default value 0 0 0 0 1 0 t t c 1 skewt h 5 1 0 clock control-1 register definition bit r/w bit 0 ~ bit 5 skewt h 0 skewt h 5 skew detection t h reshold r/w set the th reshold value for vt r skew detection. t h reshold value = [skewt h 5:skewt h 0] bit 6 bit 7 clock t r ansition t i me constant ttc 0 ttc 1 t i me constant for clock mode transition. 0 : slow est 3 : fastest register name definition clock control-2 register ( r / w ) [ sub a ddress 0x37 ] t h is register controls the clock t r ansition time in auto clock m ode w h ich is set by [ bit 7 : bit 6 ] of the auto select contro l 2 register ( 0x09 ). su b a d d r ess 0x37 defau l t valu e : 0x7c bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lnf r t h 7 l n f r t h 6 lnf r t h 5 l n f r t h 4 lnf r t h 3 lnf r t h 2 l n f r t h 1 lnf r t h 0 default value 1 1 1 1 0 0 0 1 clock control-2 register definition bit register name r/w bit 0 ~ bit 7 lnf r t h 0 lnf r t h 7 lint to f r ame t h reshold level control bit r/w t he threshold parameter from line-lock clock mode to f r ame-lock clock mode. definition rev.0 92 2003/01
asahi kasei [AK8850] clock control- 3 register ( r / w ) [ sub a ddress 0x38 ] t h is register controls the clock t r ansition time in auto clo ck mode w h ich is set by [ bit 7 : bit 6 ] of the auto select control 2 register ( 0x09 ). su b a d d r ess 0x38 defau l t valu e : 0x3c bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f r lnt h 7 f r lnt h 6 f r lnt h 5 f r lnt h 4 f r lnt h 3 f r lnt h 2 f r lnt h 1 f r lnt h 0 default value 0 0 1 1 1 0 0 1 clock control 3 register definition bit register name r/w bit 0 ~ bit 7 f r lnt h 0 frl n t h 7 f r ame to line t h reshold level control bit r/w t he threshold parameter from f r ame-lock clock mode to line-lock clock mode. definition clock control-4 register ( r / w ) [ sub a ddress : 0x39 ] t h is register controls the clock t r ansition time in auto clock m ode w h ich is set by [ bit 7 : bit 6 ] of the auto select contro l 2 register ( 0x09 ). su b a d d r ess 0x39 defau l t valu e : 0xdc bit 7 bit 6 bit 4 bit 3 bit 2 bit 1 bit 0 frfx t h 7 f r f x t h 6 frfx t h 5 f r f x t h 4 frfx t h 3 frfx t h 2 f r f x t h 1 frfx t h 0 default value 1 1 0 1 1 1 0 0 bit 5 clock control 4 register definition bit register name r/w definition bit 0 ~ frfx t h 0 bit 7 frfx t h 7 f r ame to f i x clock t h reshold level control bit r/w t he threshold parameter from f r ame-lock clock mode to f i xed clock mode. clock control-5 register ( r / w ) [ sub a ddress 0x3a ] t h is register controls the clock t r ansition time in clock auto mode set by ( bit 7 : bit 6 ) of the auto select control 2 register ( 0x09 ). su b a d d r ess 0x3a defau l t valu e : 0x04 bit 7 bit 6 bit 4 bit 3 bit 2 bit 1 bit 0 f x lnt h 6 f x lnt h 5 f x lnt h 4 f x lnt h 2 f x lnt h 1 f x lnt h 0 default value 0 0 0 1 0 0 0 0 bit 5 f x lnt h 7 f x lnt h 3 clock control 5 register definition bit register name r/w definition bit 0 ~ bit 7 f x lnt h 0 fx l n t h 7 f i x clock to line t h reshold level control bit r/w t he threshold paramet er for sw itching betw een the f i xed clock and line-lock clock modes. rev.0 93 2003/01
asahi kasei [AK8850] pll control register ( r / w ) [ sub a ddress 0x46 ] pll control register. su b a d d r ess 0x46 defau l t valu e : 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r e s e r v e d lpgaut o l p g 3 l p g 2 l p g 1 l p g 0 l p g m 1 l p g m 2 default value 0 0 0 0 0 0 0 0 pll control register definition bit register name r/w definition bit 0 bit 1 lpgm2:lpgm 1 loop gain control bit r/w f r ame lock mode ec gain lpgm[1:2] = 00 : x 1 (default 01 : x 2 10 : x 4 11 : x 8 bit 2 bit 5 lpg0:lpg3 loop gain control bit r/w lpg[1:0] line lock mode ec gain[1:0] 00 : x 1 (default 10 : x 4 lpg[3] gm gain 01 : x 1/2 11 : x 2 lpg[2] cp gain 0 : x 1 (default 1 : x 2 0 : x 1 (default) 1 : x 2 lpgaut o loop gain auto bit r/w 1 : auto in case of auto mode setting, lpg2 and lpg3 settings are ignored and the cp and gm gains are sw itched automat ically depending on the pll mode. cp x 1 (low ), gm : x1 (low ) f r ame-lock mode : cp : x 2 (high) , gm : x 2 (high) reserved bit r/w reserved bit 6 0 : manual default line-lock mode: bit 7 reserved rev.0 94 2003/01
asahi kasei [AK8850] pll da c set register ( r / w ) [ sub a ddress 0x47 ] pll control register. su b a d d r ess 0x47 defau l t valu e : 0x80 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p l l d a c i 7 p l l d a c i 6 p l l d a c i 5 p l l d a c i 4 p l l d a c i 3 p l l d a c i 2 p l l d a c i 1 p l l d a c i 0 default value 1 0 0 0 0 0 0 0 pll dac set register definition bit register name definition bit 0 bit 7 r/w adjust the external vc xo center frequency w i th this register. lsb is alw a y s disabled. plldaci0 plldaci7 pll dac input bit r/w rev.0 95 2003/01
asahi kasei [AK8850] rev.0 96 2003/01 9. sy stem connection example 39 ? ? ?
asahi kasei [AK8850] 10. package 100pin lqf p lead frame material c u 16.0
asahi kasei [AK8850] 1 1 . marking 1 a k8850 1) akm : akm logo 2) AK8850 : marketing code 3) xxxxxxx ( 7digit s ) : dat e code 4)
asahi kasei [AK8850]

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